TMS320F28377D: SPI with FIFO enabled and having overflow stops triggering reception ISR

I am having problems with the reception of the SPI. The reception ISR is not triggering after an OVERFLOW.

I am using a Master, sending data continuously in packets of 10 Bytes. I am working with FIFO enhancements enable

and the nesting in the SPI reception is allowed due to there is a control execution with higher priority.

The system is working although I receive some overflows. So, when I receive an RXFFOVF I reset the FIFO, writing 0, 1 to RXFIFORESET

and I am aware some data will be lost, but the master will send it again.

The problem appears after some time working, suddenly the reception ISR is not trigger. If I check the peripheral registers, the OVERFLOW is set and the RXFFST is 16.

As I reset the RXFIFO in the ISR and it is not called anymore, the SPI reception is not recovered.

First, I suspect in the place where I reset and clear the overflow, but I have tried in all the places, any idea on why the ISR stops triggering?

This is the reception code:

// INIT

// Enabled SPI FIFO registers

SpicRegs.SPIFFTX.all=0xE040;    //Enable enhancement, INT disabled, clear Tx INT flag

SpicRegs.SPIFFRX.bit.RXFFIENA = 1;     // Rx FIFO INT Enable

SpicRegs.SPIFFRX.bit.RXFFIL = RX_FIFO_LEVEL; // FIFO INT Level buffer

SpicRegs.SPIFFCT.all=0x00;             //Without delay

SpicRegs.SPIBRR.all =BAUDRATE;  // Baudrate 12.5MHz;

SpicRegs.SPICCR.bit.SPICHAR = WORD_BIT_NUMBER-1; // Set number of bits to transmit or recive

SpicRegs.SPISTS.all=0x0000;            // Reset status

SpicRegs.SPIFFRX.bit.RXFIFORESET = 1;    // Re-enable RX FIFO

SpicRegs.SPICCR.bit.SPISWRESET=1;  // Enable SPI

//  SPIC SLAVE **********************************
__interrupt void receiveEpcMessageSpiDrv(void)
{
    uint16_t rxShiftedData;
    uint16_t fifoReceived;
    uint8_t word;

    EINT;   // Allow higher priority interrupts.
    fifoReceived = SpicRegs.SPIFFRX.bit.RXFFST;

    for(word = 0; word < fifoReceived; word++)

   {
        //READ RX FIFO data from the SPIRXBUF
        rxShiftedData = SpicRegs.SPIRXBUF<<(16-WORD_BIT_NUMBER);

        if(circBuffer.validData < CIRC_BUFFER_MAX_LEN)
            {
            circBuffer.validData++;
            circBuffer.spiRxBuff[circBuffer.writeBuffP] = rxShiftedData>>(16-WORD_BIT_NUMBER);
            circBuffer.writeBuffP = (circBuffer.writeBuffP+1) & (CIRC_BUFFER_MAX_LEN-1);
            }

        }
    DINT;
    if(SpicRegs.SPIFFRX.bit.RXFFOVF)
    {
        SpicRegs.SPIFFRX.bit.RXFIFORESET = 0;
        PIN_TOGGLE(1);
        while(SpicRegs.SPIFFRX.bit.RXFFOVF == 1);
        SpicRegs.SPIFFRX.bit.RXFIFORESET = 1;
    }

    SpicRegs.SPIFFRX.bit.RXFFINTCLR=1;  // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=PIEACK_GROUP6; // Issue PIE ack
   }