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TMS320F28388D: IIC start bit and device address transmit issue

Cherry Zhou
Mastermind 22235 points

Part Number: TMS320F28388D
Other Parts Discussed in Thread: MCT8316A

Hi team,

Here's an issue from the customer may need your help:

1) When does the IIC peripheral of the C2000 family of controllers generate the start bit on the bus? Does the start bit immediately generate when I2caRegs.I2CMDR.bit.STT = 1;?

2) Is the transmission of device addresses implemented by the IIC peripheral itself? Is the device address automatically sent when the start bit is generated?

3) Is there any way to control the time interval between the device address and the first byte that follows?

Application issue:

Currently using the IIC of 28388D to control the MCT8316A, the IIC communication of the MCT8316A has the following special requirements:

This device requires a 100US delay between data when IIC is communicating. Should be possible in the case of data transmission; However, if the slave receives multiple bytes of data, the IIC should automatically generate the required SCL based on the value in CNT, and the slave transmits the data to the master based on the SCL. Right? So there should be no way to change the way SCL is sent?

The sending mechanism of the device address is not described in detail in the manual for the C2000 family. If the IIC peripheral automatically controls the sending device address, is it not possible to add a 100US delay between the device address and the first byte that follows?

How does C2000's IIC achieve 100US delay between transmission bytes?

Could you help check this case? Thanks.

Best Regards,

Cherry

  • 0
    TI__Guru 55700 points

    Cherry,

    1) If I2C bus is IDLE, setting STT bit will indeed generate START condition immediately

    2) Yes, when START condition is generated, slave address stored in I2CSAR is automatically transmitted.

    3) From I2C hardware perspective, there is no way to generate delays between each by transfer. However, you can introduce the 100us delay using software.

    If you use non-repeat mode, I2C doesn't generate STOP condition until I2CCNT number of transactions are complete.

    In repeat mode, 2CCNT register isn't used and number of I2C byte transaction is software configurable. In either of these modes, you can introduce software delay if you don't use FIFO. If FIFO contents are prefilled, all the contents in FIFO will be transmitted and you cannot use software to introduce delays between byte transactions.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Mastermind 22235 points

    Hi Manoj,

    Thanks for your help.

    When Master Send, CNT is set to 0, no FIFO is used, and RM mode is not used. When the STT is set, the NACK bit is detected in while, and if no response is received from the slave, the NACK bit is always set high and waiting. A NACK of 0 indicates that an ACK was received from the slave, exiting while. Then the delay is 100US, at which point the device address is sent and the wait is 100US. Next, data is transmitted, data is written to the DXR register, and then the NACK bit is used to determine if the transmission is complete, adding a 100US delay after the transmission is complete. (The process of sending multiple data is the same)

    At Master Send, CNT is set to 0 and RM mode is not used. Is this right? If not, then the correct practice should be RM mode, instead of setting the value for CNT?

    Thanks and regards,

    Cherry

  • 0 in reply to Cherry Zhou
    TI__Guru 55700 points

    Cherry,

    Is this a duplicate thread? I seems to pretty much ask the same question.

    Are you both supporting the same customer problem?

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1110088/tms320f28388d-how-to-add-100us-delay-between-bytes-when-reading-slave-device-data

    When REPEAT mode is enabled, I2CCNT register value becomes don't care and allows the software to completely control the number of I2C transaction. Setting I2CCNT = 0 doesn't disable the FIFO. We have specific disable bit in FIFO for that.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Mastermind 22235 points

    Hi Manoj,

    Thanks and I've confirmed with my co-worker, we're supporting the same customer. Since  this thread is more detailed on the issue, we could close this thread here and continue discuss the case on another thread. Thanks for your support again.

    Regards,

    Cherry