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TMS320F280039C: Missing the VCD file when building TI CLB examples

Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE

Dear Champs,

I am asking this for our customer.

I followed the post and set both the variables CLB_DEBUG and GENERATE_DIAGRAM to 1.

Environment:

CCS 11.1.

C2000ware V4.01

CLB examples like clb_ex8_external_signal_AND_gate

I could see the block diagram (clb.html), but I could not see its corresponding .vcd.

TDM compiler is the specific version from the doc (https://www.ti.com/lit/ug/spruir8a/spruir8a.pdf?ts=1655696716156)

“tdm-gcc” from the following link: https://sourceforge.net/projects/tdm-gcc/files/TDMGCC%20Installer/tdm64-gcc-5.1.0-2.exe/download

It's weird that the simulation folder (for CLB) is empty.

There were some errors related to building the simulation files, but I could not understand why.

Would you please help clarify?

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**** Build of configuration CPU1_RAM for project clb_ex8_external_signal_AND_gate ****
"C:\\ti\\ccs1110\\ccs\\utils\\bin\\gmake" -k -j 8 all -O
Building file: "../clb_ex8_external_signal_AND_gate.syscfg"
Invoking: SysConfig
"C:/ti/ccs1110/ccs/utils/sysconfig_1.11.0/sysconfig_cli.bat" -s "C:/ti/c2000/C2000Ware_4_01_00_00/.metadata/sdk.json" -d "F28003x" --script "C:/Users/a0388935/TI Drive/TI/Work/20220620_CCS1110_F280039CC_CLB/clb_ex8_external_signal_AND_gate/clb_ex8_external_signal_AND_gate.syscfg" -o "syscfg" --package 100PZ --part F28003x_100PZ --compiler ccs
Running script...
Validating...
Generating Code (clb_ex8_external_signal_AND_gate.syscfg)...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\board.c...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\board.h...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\pinmux.csv...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb_config.h...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb_config.c...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb.dot...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb_sim.cpp...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.cmd.genlibs...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.opt...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.c...
Writing C:\Users\a0388935\TI Drive\TI\Work\20220620_CCS1110_F280039CC_CLB\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.h...
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Wayne Huang

  • Hi Wayne,

    I attempted to build the same CLB example (ex8) and my simulation folder and simulation_output.exe file was able to generate successfully. Here is the build output for reference.

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    **** Build of configuration CPU1_RAM for project clb_ex8_external_signal_AND_gate ****
    "C:\\ti\\ccs1100\\ccs\\utils\\bin\\gmake" -k -j 8 all -O
    Building file: "../clb_ex8_external_signal_AND_gate.syscfg"
    Invoking: SysConfig
    "C:/ti/ccs1100/ccs/utils/sysconfig_1.13.0/sysconfig_cli.bat" -s "C:/ti/c2000/C2000Ware_4_01_00_00/.metadata/sdk.json" -d "F28003x" --script "C:/Users/a0488298/CCS_workspaces/workspace_v11_CLB_VCD/clb_ex8_external_signal_AND_gate/clb_ex8_external_signal_AND_gate.syscfg" -o "syscfg" --package 100PZ --part F28003x_100PZ --compiler ccs
    Running script...
    Validating...
    Generating Code (clb_ex8_external_signal_AND_gate.syscfg)...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\board.c...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\board.h...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\pinmux.csv...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb_config.h...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb_config.c...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb.dot...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\clb_sim.cpp...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.cmd.genlibs...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.opt...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.c...
    Writing C:\Users\a0488298\CCS_workspaces\workspace_v11_CLB_VCD\clb_ex8_external_signal_AND_gate\CPU1_RAM\syscfg\c2000ware_libraries.h...
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    After comparing your output with my output, I see this is the first significant difference

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    makefile:177: recipe for target 'post-build' failed
    A subdirectory or file C:/Users/a0388935/TI Drive/TI/Work/20220620_CCS1110_F280039CC_CLB/clb_ex8_external_signal_AND_gate/CPU1_RAM/simulation already exists.
    gmake[2]: [post-build] Error 1 (ignored)
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    followed by a number of 'g++ error' that prevent the simulation from building. 

    Can you attempt the following steps and let me know if you get the same issue?

    1. Create a new CCS workspace.

    2. Import CLB ex8 from C2000Ware 4.01.00.00

    3. Change the CLB_DEBUG and GENERATE_DIAGRAM values in project settings.

    4. Right-click project and select "Rebuild Project"

    Under the CPU1_RAM folder, there should be another folder title "simulation" which includes a simulation_output.exe file. Do you see this?

    Regards,

    Peter

  • Dear Peter,

    I had used the same procedures like you in the first post, and even I tried again with a new workspace, it did not work.

    However, I just found the name length of workspace (including the folder names I used) was the root cause.

    After changing to a new workspace with much shorter name (including the folder names I used), I find it works now.

    It's possible that GNU g++ cannot accept such long names and it does not warn this either.

    Thank you for your support.