• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 81 subscribers
  • Views 186 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS320F2812: CS2# stays low after few transactions on booting

TMS320F2812: TMS320F2812 Chip select CS2 stops and stays high after a few transition.

Vishnu Jayaraj
Prodigy 10 points
Part Number: TMS320F2812

TMS320F2812 is designed to boot from external boot space. Initially the bootloader is loaded to FPGA Dual port ram by ARM processor. The boot vector is perfectly fetched from FPGA using CS6&7 and it jumps to the bootloader location (using CS2) in FPGA dual port ram and starts file fetch. Our observation is once the boot-loader is fetched and during its execution the CS2 stops transition and stay high. This issue occurs randomly in some PCBAs only. Is there any known issues and solutions similar to this?

  • 0
    TI__Guru* 93985 points

    Are there PCBs that never show this problem? Is the problem seen only in some PCBs? Even on those PCBs, what is the rate of occurrence? There are a few errata pertaining to XINTF. Have you checked if those apply to your design? See www.ti.com/lit/SPRZ193.

  • 0 in reply to Hareesh Janakiraman
    Prodigy 10 points

    We have taken care for XINTF timings. Our PCBA is designed to run two FPGA projects one at a time controlled by a switch mechanism. One code works without any issues in multiple PCBAs. While we run the other project the external boot fails and in some PCBs the expected clock-out 75Mhz shows 150Mhz/No clock out/75Mhz. This un-expected clock behavior differs from PCBA to PCBA. In the bootloader, clock out is configured followed by a FPGA register write, even though the clock configuration failed we got that FPGA register write successful and CS2 stops transition. For both projects the external boot procedure is identical.

  • 0 in reply to Vishnu Jayaraj
    TI__Guru* 93985 points

     Vishnu,

             It is extremely difficult to debug such issues without access to the schematics/hardware and a thorough knowledge of the design from both H/W & S/W perspective. With the information available, I am afraid I cannot be of much help.

  • 0 in reply to Hareesh Janakiraman
    Prodigy 10 points

    Hi Hareesh,

          PFA, We were able to solve the above issues with some code changes. Our observation is on all the working PCBAs after bootloader fetching, the execution starts at a particular time in our case it is 190mS. In one PCBA  at this 190mS instead of file execution, again the boot vector fetch is occurring but vector fetch address is wrong after first fetch. This retry happens for 10seconds and CS6&7 stays high and CS2 stays low. What could be the reason for this retry? (Note:Green-CS2,Pink-CS6&7)

  • 0 in reply to Vishnu Jayaraj
    TI__Guru* 93985 points

    Vishnu,

        As explained before, remote debug of such complex issues without access to all the design information is not practical. Issues like this warrant hands-on debug. I regret I am unable to help.