TMS320F28379D: Add PI Controller using CLA to FreeRTOS project running on C28x CPU 1

Hi Rashmitha,

We do not have a F2837xD based example. Here is a CLA based PI example in F28069 device in C2000ware. 

C:\ti\c2000\C2000Ware_4_01_00_00\libraries\control\DCL\c28\examples\F28069_PI_CLA

Best regards,

Han

Hi Hans Zhang,

Thanks for your reply.

I am referring to the example that you suggested and also referring to CLA example given for F2837xD to understand the linker file changes needed.

I see that DCLCLA.h file gives below prototypes for implementing 2 parallel PID loops

extern float32_t DCL_runPID_L1(DCL_PID_CLA *p, float32_t rk, float32_t yk, float32_t lk);

extern float32_t DCL_runPID_L2(DCL_PID_CLA *p, float32_t rk, float32_t yk, float32_t lk);

I would like to know if its possible to use 3 PI loops at the same time.

Also, are there any examples for multiple PI loops running simultaneously?

Regards,

Rashmitha

Hi Hans Zhang

Thanks for your reply. Sure I will use multiple instances instead of L1/L2.

I am getting some warnings w.r.t. the changes made in the linker file as below.

My linker file is as given below, I added parts of the linker file from the CLA included projects into my original linker file

#ifdef CLA_C
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800	//2kb
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASH_B_C_D           : origin = 0x082000, length = 0x006000	/* on-chip Flash */
//   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
//   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
//   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */ //8kb
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

   CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASH_B_C_D      PAGE = 0, ALIGN(8)
//   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
//   .text               : >> FLASHB_C | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
	 .text               : >> FLASH_B_C_D | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASH_B_C_D      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */

#if defined(__TI_EABI__)
   .init_array         : > FLASH_B_C_D,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASH_B_C_D,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

   Filter_RegsFile     : > RAMGS0,	   PAGE = 1

   SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   ramgs0           : > RAMGS0,     PAGE = 1
   ramgs1           : > RAMGS1,     PAGE = 1
   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
   Cla1DataRam0	    : > RAMLS1,	  PAGE = 0
   Cla1DataRam1	    : > RAMLS2,	  PAGE = 0
   Cla1DataRam2	    : > RAMLS3,	  PAGE = 0

    /* CLA specific sections */
    
   #if defined(__TI_EABI__)
   		Cla1Prog    : LOAD = FLASHE,
                      RUN = RAMLS4,
                      LOAD_START(Cla1funcsLoadStart),
                      LOAD_END(Cla1funcsLoadEnd),
                      RUN_START(Cla1funcsRunStart),
                      LOAD_SIZE(Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(8)
   #else
      	Cla1Prog    : LOAD = FLASHE,
                      RUN = RAMLS4,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      LOAD_SIZE(_Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(8)
   #endif
   
   #ifdef CLA_C
   /* CLA C compiler sections */
   //
   // Must be allocated to memory the CLA has write access to
   //
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 0

   .scratchpad      : > RAMLS1,       PAGE = 0
   .bss_cla		    : > RAMLS1,       PAGE = 0
   .const_cla	    : > RAMLS1,       PAGE = 0
#endif //CLA_C

   Cla1Prog         : > RAMLS4, PAGE=0

   CLADataLS0		: > RAMLS0, PAGE=0
   CLADataLS1		: > RAMLS1, PAGE=0

   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHE,
                                 RUN = RAMLS0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHE,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs            : LOAD = FLASHE,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
    #endif

#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

   /* The following section definition are for SDFM examples */
   Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
   Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
   Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
   Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
   Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Could you please guide me to get rid of the warnings above? Is there some other .cmd file that needs to be included for CLA support?

The .out file generated with this linker file is unable to show any symbols when loaded on the processor. 

Could you also point out if there is any mistake in the linker file which has resulted in symbols missing? Because the original linker file before adding CLA related lines was working fine and showing symbols.

Regards,

Rashmitha

Hi Rashmitha,

The linker command file content is wrapped inside #ifdef CLA_C. Please define the CLA_C symbol in the linker settings.

Here is a related post:

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/673739/ccs-tms320f28377s-creating-output-section-scratchpad-without-a-sections-specification-cla_general?ReplyFilter=Answers&ReplySortBy=Answers&ReplySortOrder=Descending

Thanks,

Ashwini

Hi Ashwini Athalye,

Thanks for your response. I defined the symbol in Command File preprocessing and even tried removing the #ifdefs.

The symbols are still missing. When I load the code I see below screen in the debug window

Regards,

Rashmitha

Hi Rashmitha,

1. Please check if the application is being built for debug with debug symbols enabled in the compiler settings

2. Can you try loading symbols from CCS menu?

Thanks,
Ashwini

Hi Ashwini Athalye,

1. 

2. When I loaded separately from the CCS menu, I can see the symbols. Why is this happening? The project was loading the symbols on it own before adding the CLA

Although I don't see any symbols for the CLA

Regards,

Rashmitha

Hi Rashmitha, the CLA is at this time pointing to a location where there is no code hence no symbols are appearing. When the CLA starts executing and if it halts at a location where there is real code, symbols should show up.

Thanks,

Ashwini

Hi Ashwini Athalye,

I am now using 2837xD_FLASH_CLA_lnk_cpu1.cmd from C:\ti\c2000\C2000Ware_4_00_00_00\device_support\f2837xd\common\cmd

I have added a few lines in this to add my sections.

I am using below functions to configure the CLA

//
// configClaMemory - Configure CLA memory
//
void configClaMemory(void)
{
#ifdef _FLASH
	extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
	//
	// Copy over code from FLASH to RAM
	//
	memcpy((uint32_t*) &Cla1funcsRunStart, (uint32_t*) &Cla1funcsLoadStart,
			(uint32_t) &Cla1funcsLoadSize);
#endif //_FLASH

#ifdef CPU2
    //
    // Enable CPU2 clocking at the sys clock level
    //
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1);
#endif //CPU2

	//
	// Initialize and wait for CLA1ToCPUMsgRAM
	//
	MemCfg_initSections(MEMCFG_SECT_MSGCLA1TOCPU);
	while (!MemCfg_getInitStatus(MEMCFG_SECT_MSGCLA1TOCPU))
	{
	}

	//
	// Initialize and wait for CPUToCLA1MsgRAM
	//
	MemCfg_initSections(MEMCFG_SECT_MSGCPUTOCLA1);
	while (!MemCfg_getInitStatus(MEMCFG_SECT_MSGCPUTOCLA1))
	{
	}

	//
	// Select LS4RAM to be the programming space for the CLA
	// First configure the CLA to be the master for LS4 and then
	// set the space to be a program block
	//
	MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS4, MEMCFG_LSRAMMASTER_CPU_CLA1);
	MemCfg_setCLAMemType(MEMCFG_SECT_LS4, MEMCFG_CLA_MEM_PROGRAM);

	//
	// Next configure LS0RAM and LS1RAM as data spaces for the CLA
	// First configure the CLA to be the master for LS0(1) and then
	// set the spaces to be code blocks
	//
	MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMMASTER_CPU_CLA1);
	MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_DATA);

	MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMMASTER_CPU_CLA1);
	MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_DATA);
}


//
// CLA_initCpu1Cla1 - Initialize CLA1 task vectors and end-of-task interrupts
//
void CLA_initCpu1Cla1(void)
{
	//
	// Compute all CLA task vectors
	// On Type-1 CLAs the MVECT registers accept full 16-bit task addresses as
	// opposed to offsets used on older Type-0 CLAs
	//
	EALLOW;
	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_1, (uint16_t) &Cla1Task1);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_2, (uint16_t) &Cla1Task2);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_3, (uint16_t) &Cla1Task3);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_4, (uint16_t) &Cla1Task4);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_5, (uint16_t) &Cla1Task5);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_6, (uint16_t) &Cla1Task6);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_7, (uint16_t) &Cla1Task7);
//	CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_8, (uint16_t) &Cla1Task8);

	//
	// Enable the IACK instruction to start a task on CLA in software
	// for all  8 CLA tasks. Also, globally enable all 8 tasks (or a
	// subset of tasks) by writing to their respective bits in the
	// MIER register
	//
	CLA_enableIACK(CLA1_BASE);
	CLA_enableTasks(CLA1_BASE, CLA_TASKFLAG_ALL);

	//
	// Configure the vectors for the end-of-task interrupt for all
	// 8 tasks
	//
	Interrupt_register(INT_CLA1_1, &cla1Isr1);
	Interrupt_register(INT_CLA1_2, &cla1Isr2);
	Interrupt_register(INT_CLA1_3, &cla1Isr3);
	Interrupt_register(INT_CLA1_4, &cla1Isr4);
	Interrupt_register(INT_CLA1_5, &cla1Isr5);
	Interrupt_register(INT_CLA1_6, &cla1Isr6);
	Interrupt_register(INT_CLA1_7, &cla1Isr7);
	Interrupt_register(INT_CLA1_8, &cla1Isr8);

	//
	// Enable CLA interrupts at the group and subgroup levels
	//
	Interrupt_enable(INT_CLA1_1);
	Interrupt_enable(INT_CLA1_2);
	Interrupt_enable(INT_CLA1_3);
	Interrupt_enable(INT_CLA1_4);
	Interrupt_enable(INT_CLA1_5);
	Interrupt_enable(INT_CLA1_6);
	Interrupt_enable(INT_CLA1_7);
	Interrupt_enable(INT_CLA1_8);
}

And then in a .cla file I have the CLA Task defined as below

__interrupt void Cla1Task1(void)
{
	__mdebugstop();

// run the PI controller
	uk1 = DCL_runPI_L1(&pi1, rk1, yk1);
	uk2 = DCL_runPI_L1(&pi2, rk2, yk2);
	uk3 = DCL_runPI_L1(&pi3, rk3, yk3);

	__mnop();

}

I can compile the project without any errors or warnings. I can see CPU and CLA running. The control reaches the CLA Task and stops there on every run even when there is no breakpoint.

How to get past this inbuilt breakpoint like behavior?

Regards,

Rashmitha

Hi Rashmitha,

IN the Cla1Task1 C code snippet above I see that the code includes _mdebugstop() instruction. This is a software breakpoint instruction and hence the CLA task is halting each time it executes.

Thanks,
Ashwini