TMS320F28069M: Changing TBPRD value of slave EPWMs while sync enabled

Hi Syed,

SYED MOHAMMAD MAAZ said:

EPWM1 is set at TBPRD=4500(10Khz) so if I change the EPWM2 TBPRD value =9000(5Khz).The action qualifier does not output anything. They work only when they are the same value or PHSEN is disabled(which I don't want).

Can you please provide your initialization code for EPWM1 and EPWM2 so I can check what count mode you are using and what your action qualifier settings are? When you say "the action qualifier does not output anything", you mean you see EPWM2 at a constant low state?

Best Regards,

Marlyn

void
InitEPwm1Example()
{
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO ; //
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm1Regs.TBPHS.half.TBPHS = 0;

EPwm1Regs.TBPRD = 4500; //9000 // Set timer period 801 TBCLKs
// EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter

//
// Set Compare values
//
EPwm1Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm1Regs.CMPB = 0; // Set Compare B value

//
// Setup counter mode
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

//
// Setup shadowing
//
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on event A, down count

EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm1Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM1B on event B, down count

//
// Interrupt where we will change the Compare Values
//
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRDZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate INT on 5th event

//
epwm1_info.EPwmRegHandle = &EPwm1Regs;

}

void
InitEPwm2Example()
{
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Pass through
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBPHS.half.TBPHS = 0;

EPwm2Regs.TBPRD = 9000; //4500 // Set timer period 801 TBCLKs
EPwm2Regs.TBCTR = 0x0000; // Clear counter

//
// Set Compare values
//
EPwm2Regs.CMPA.half.CMPA = 2000; // Set compare A value
EPwm2Regs.CMPB = 0; // Set Compare B value

//
// Setup counter mode
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

//
// Setup shadowing
//
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // Clear PWM1A on event A, down count

EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Set PWM1B on event B, up count
EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Clear PWM1B on event B, down count

epwm2_info.EPwmRegHandle = &EPwm2Regs;

}

EPWM2 is constantly low when TBPRDs are different.
as soon as I change them to the same value it starts working or if I disable sync it again starts to work.