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CCS/TMS320F28379D: Cannot synchronize different EPWM frequencies

Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hello,

I am trying to synchronize two EPWM with different frequencies. EPWM1 is used as mater to synchronize EPWM2. EPWM1 is running at 1.250 kHz and EPWM2 is running at 2.500 kHz. When I view these signals on oscilloscope, the EPWM2 signal is forced at 1.2500 kHz with duty cycle equal to EPWM1 and a random phase shift. If I disable the EPWM1 module, EPWM2 is running at the correct frequency i.e. 2.500 kHz. In addition to this, when both modules are configured at same frequencies, then I am observing correct frequency with desired phase shift. Please find below the code snippet:

void InitEpwm1()

{

       EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
       EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;   // Clock ratio to SYSCLKOUT
       EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

       //Calculate TBPRD Value assuming EPWMCLKDIV default value equal to 2
       TBPRD  =  100000000/(12500* 2 *2);

       // Setup TBCLK
       EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;        // Count up

       EPwm1Regs.TBPRD = TBPRD;
    
      EPwm1Regs.TBCTL.bit.PHSEN   = TB_DISABLE;         // Enable/Disable phase loading

       EPwm1Regs.TBCTR             = 0x0000;      // Clear counter

       // Set actions
       EPwm1Regs.AQCTLA.bit.ZRO      = AQ_SET;       // Clear PWM2A on Down compare
       EPwm1Regs.AQCTLA.bit.CAU      = AQ_CLEAR;         // set PWM2A on Up compare

       EPwm1Regs.AQCTLB.bit.ZRO      = AQ_CLEAR;         // Set PWM2B on Down compare
       EPwm1Regs.AQCTLB.bit.CBU      = AQ_SET;       // Clear PWM2B on Up compare


    
      EPwm1Regs.TBPHS.bit.TBPHS   =  0;   // Phase
}

void InitEpwm2()

{


       EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;   // Clock ratio to SYSCLKOUT
       EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

       //Calculate TBPRD Value assuming EPWMCLKDIV default value equal to 2
       TBPRD  =  100000000/(2500* 2 *2);  

       // Setup TBCLK
       EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;        // Count up

       EPwm2Regs.TBPRD = TBPRD;
    
      EPwm2Regs.TBCTL.bit.PHSEN   = TB_ENABLE;         // Enable/Disable phase loading

       // Set actions
       EPwm2Regs.AQCTLA.bit.ZRO      = AQ_SET;       // Clear PWM2A on Down compare
       EPwm2Regs.AQCTLA.bit.CAU      = AQ_CLEAR;         // set PWM2A on Up compare

       EPwm2Regs.AQCTLB.bit.ZRO      = AQ_CLEAR;         // Set PWM2B on Down compare
       EPwm2Regs.AQCTLB.bit.CBU      = AQ_SET;       // Clear PWM2B on Up compare



       EPwm2Regs.TBCTR             = 0x0000;      // Clear counter
    
      EPwm2Regs.TBPHS.bit.TBPHS   =  0;   // Phase
}

  • When you configure PWM module 1 as the master this way, it generates a SYNC pulse each time your get a counter zero. This happens at the PWM frequency of 1.25 kHz. PWM module 2 sees those pulses and resets its counter to zero each time. As you've configured PWM2 to run at half the frequency of PWM1, its counter always resets before it reaches it's own period setting and the modules end up at the same frequency. To sync this way, you'll need to have PWM1 at the lower frequency.

    Regards,

    Richard
  • Could you re-check these period calculations please? The first is a factor of 5 bigger, rather than half the size.

    PWM1:
    TBPRD = 100000000/(12500* 2 *2);

    PWM2:
    TBPRD = 100000000/(2500* 2 *2);

    Regards,

    Richard
  • Hi,

    You can just swap the PWM configuration and try to get the desired result.
    i.e., use PWM2 with higher frequency and PWM1 with lower frequency and rest of the configuration can be same as above.
  • Hello,

    I checked my code and it seems that there must have been a typo while copying the code (sorry about that). PWM1 is in fact TBPRD = 100000000/(1250* 2 *2); in my code. When I went into the online debugger, I observed that the value of TBPHS was getting more than the value of TBPRD of EPWM2. After fixing this, I am getting the correct frequency and phase shift.

    Thanks for the help!

    Prateek Jain