TMS320F28379D: epwm synchronization questions

Hi, I'm learning 28379D one day workshop and have read the following codes: 

void InitEPwm1(void)
{
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBPRD = period1; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // SYNC output on CTR = 0

// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;

// Set Compare values
EPwm1Regs.CMPA.bit.CMPA = dutyCycle1; // Set compare A value

// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = 2; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAU = 1; // Clear PWM1A on event A, up count
}

void InitEPwm5(void)
{
// Setup TBCLK
EPwm5Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm5Regs.TBPRD = PWM1_PERIOD; // Same period as PWM1
EPwm5Regs.TBCTL.bit.PHSEN = 1; // Enable phase loading
EPwm5Regs.TBPHS.bit.TBPHS = phaseOffset5; // Phase
EPwm5Regs.TBCTR = 0x0000; // Clear counter
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = 0;

// Setup shadow register load on ZERO
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;

// Set Compare values
EPwm5Regs.CMPA.bit.CMPA = dutyCycle5; // Set compare A value

// Set actions
EPwm5Regs.AQCTLA.bit.ZRO = 2; // Set PWM1A on Zero
EPwm5Regs.AQCTLA.bit.CAU = 1; // Clear PWM1A on event A, up count
}

It's said that EPWM5 SYNC input is from EPWM1 SYNCOUT, but I don't understand. From below picture, EPWM5 SYNC input can only be from EPWM4 SYNCOUT, and EPWM4 SYNC input is selected by SYNCSELEPWM4SYNCIN among EPWM1SYNCOUT, EXTSYNCIN1, EXTSYNCIN2.