TMS320F28379D: Synchronization of ePWMS

void InitEPwm1Example()
{

    // Setup TBCLK
    EPwm1Regs.TBPRD = TBPFC;          // Set timer period 801 TBCLKs
    EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm1Regs.TBCTR = 0x0000;                      // Clear counter

    // Set Compare values
    EPwm1Regs.CMPA.bit.CMPA = ref_offset;    // Set c00ompare A value
    EPwm1Regs.CMPB.bit.CMPB = ref_offset;   // Set Compare B value

    // Setup counter mode
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // required to disable this master and for independent pwm generation

    // Setup shadowing
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;  // Load on Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set actions
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; //AQ_SET;         // When sine<triangle set lower switch 51
    EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; //AQ_CLEAR;   // Clear PWM1A on event A, down count

    EPwm1Regs.AQCTLB.bit.CBU = AQ_SET; //AQ_CLEAR;       // // When sine>triangle set upper switch 49
    EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR; //AQ_SET;     // Clear PWM1B on event B, down count

    //essentially first upper switch conducts with leg 2 lower

    // Active high complementary PWMs - Setup the deadband
    //
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBRED.bit.DBRED = EPWM1_MIN_DB;
    EPwm1Regs.DBFED.bit.DBFED = EPWM1_MIN_DB;
    EPwm1_DB_Direction = DB_UP;

    //
    // Interrupt where we will change the deadband
    //
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;      // Select INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 1;                 // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;            // Generate INT on 3rd event

    //
    // Information this example uses to keep track
    // of the direction the CMPA/CMPB values are
    // moving, the min and max allowed values and
    // a pointer to the correct ePWM registers
    //
    epwm1_info.EPwmDB_Direction = DB_UP; // Start by increasing
                                         // CMPA & CMPB
    epwm1_info.EPwmTimerIntCount = 0;             // Zero the interrupt counter
    epwm1_info.EPwmRegHandle = &EPwm1Regs;        // Set the pointer to the
                                                  // ePWM module
    epwm1_info.EPWMMAX_DB = EPWM1_MAX_DB;      // Setup min/max
    epwm1_info.EPWMMIN_DB = EPWM1_MIN_DB;      // Setup min/max

}
void InitEPwm3Example(void)
{

    // Setup TBCLK
    EPwm3Regs.TBPRD = TBDAB;          // Set timer period 801 TBCLKs
    EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
    EPwm3Regs.TBCTR = 0x0000;                      // Clear counter

    // Set Compare values
    EPwm3Regs.CMPA.bit.CMPA = dutyA_DAB;               // Set c00ompare A value
    EPwm3Regs.CMPB.bit.CMPB = dutyB_DAB;               // Set Compare B value

    // Setup counter mode
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    // Setup shadow register load on ZERO
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set Actions
    EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;            // Set PWM3A on period
    EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;   // Clear PWM3A on event B, down count

    EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;          // Clear PWM3A on period
    EPwm3Regs.AQCTLB.bit.CBD = AQ_SET;         // Set PWM3A on event A, up count

    // Active high complementary PWMs - Setup the deadband
    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm3Regs.DBRED.bit.DBRED = EPWM3_MIN_DB;
    EPwm3Regs.DBFED.bit.DBFED = EPWM3_MIN_DB;
    EPwm3_DB_Direction = DB_UP;

    // Interrupt where we will change the Compare Values
    EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm3Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event

    //
    // Information this example uses to keep track
    // of the direction the CMPA/CMPB values are
    // moving, the min and max allowed values and
    // a pointer to the correct ePWM registers
    //
    epwm3_info.EPwmDB_Direction = DB_UP; // Start by increasing
                                         // CMPA & CMPB
    epwm3_info.EPwmTimerIntCount = 0;             // Zero the interrupt counter
    epwm3_info.EPwmRegHandle = &EPwm3Regs;        // Set the pointer to the
                                                  // ePWM module
    epwm3_info.EPWMMAX_DB = EPWM3_MAX_DB;      // Setup min/max
    epwm3_info.EPWMMIN_DB = EPWM3_MIN_DB;      // Setup min/max

}
void InitEPwm6Example(void)
{

    // Setup TBCLK
    EPwm6Regs.TBPRD = TBDAB;          // Set timer period 801 TBCLKs
    EPwm6Regs.TBPHS.bit.TBPHS = phase_bridge;            // Phase is 0
    EPwm6Regs.TBCTR = 0x0000;                      // Clear counter

    // Set Compare values
    EPwm6Regs.CMPA.bit.CMPA = dutyA_DAB;               // Set c00ompare A value
    EPwm6Regs.CMPB.bit.CMPB = dutyB_DAB;               // Set Compare B value

    // Setup counter mode
    EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
    EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE;        // Disable phase loading
    EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
    EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    // Setup shadow register load on ZERO
    EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set Actions
    EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Set PWM3A on period
    EPwm6Regs.AQCTLA.bit.CAD = AQ_SET;    // Clear PWM3A on event B, down count

    EPwm6Regs.AQCTLB.bit.CBU = AQ_SET;            // Clear PWM3A on period
    EPwm6Regs.AQCTLB.bit.CBD = AQ_CLEAR;       // Set PWM3A on event A, up count

    // Active high complementary PWMs - Setup the deadband
    EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm6Regs.DBRED.bit.DBRED = EPWM3_MIN_DB;
    EPwm6Regs.DBFED.bit.DBFED = EPWM3_MIN_DB;
    EPwm6_DB_Direction = DB_UP;

    // Interrupt where we will change the Compare Values
    EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    EPwm6Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    EPwm6Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event

    //
    // Information this example uses to keep track
    // of the direction the CMPA/CMPB values are
    // moving, the min and max allowed values and
    // a pointer to the correct ePWM registers
    //
    epwm6_info.EPwmDB_Direction = DB_UP; // Start by increasing
                                         // CMPA & CMPB
    epwm6_info.EPwmTimerIntCount = 0;             // Zero the interrupt counter
    epwm6_info.EPwmRegHandle = &EPwm6Regs;        // Set the pointer to the
                                                  // ePWM module
    epwm6_info.EPWMMAX_DB = EPWM3_MAX_DB;      // Setup min/max
    epwm6_info.EPWMMIN_DB = EPWM3_MIN_DB;      // Setup min/max

}