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TMS320F280039C: issue about HLC operation when using CLB

Yale Li 李耀先
Expert 4660 points
Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE

Hi Team,

Here's an issue from the customer may need your help:

C:\ti\c2000\C2000Ware_4_01_00_00\driverlib\f28003x\examples\clb----clb_ex3_auxiliary_pwm

CLB_setHLCRegisters(myTILE1_BASE, dutyValue, 0, 0, 0);

Why can this function directly assign values to R0, R1, R2 in HLC?

The order is not supposed to be: CPU--->FIFO----->CLB's HLC?

spracl3

Thanks & Regards

Yale Li

  • 0
    TI__Mastermind 28220 points

    Hi Yale,

    Our CLB expert Peter Luong will get back to you as soon as possible, thank you for your patience.

    Luke

  • 0 in reply to Luke Jones
    TI__Mastermind 19211 points

    Hi Yale, 

    Thank you for reaching out. As mentioned in the document, the CPU has access to some registers in the CLB, including the R0, R1, R2, and R3 registers. In the design in the example3, since the only thing that is being transferred is the duty value into the match condition of the counter, the approach taken involves the following HLC and ISR actions (repeatedly)

    TRANSFER R0 VALUE INTO MATCH CONDITION -> SIGNAL HLC INTERRUPT -> (IN ISR) ASSIGN NEW DUTY VALUE INTO R0

    With the app note you mentioned, the FIFO is used to simultaneously transfer data into the load value and match value using the method CPU -> FIFO -> HLC. These are simply two approaches to performing similar data transfer actions and the difference lies in how much data you are needing to transfer at a time. Please let me know if this answered your question or if you have any other questions

    Regards,

    Peter