#include "F28x_Project.h"
#define DB_UP 1
#define DB_DOWN 0
#define COMPARE 1000
#define TBPEAK 3460
//GLOBAL
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
Uint16 EPwm1_DB_Direction;
Uint16 EPwm2_DB_Direction;
Uint16 EPwm3_DB_Direction;
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
interrupt void epwm1_isr(void);
interrupt void epwm2_isr(void);
interrupt void epwm3_isr(void);
/** * main.c */
int main(void)
{
InitSysCtrl();
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
DINT;
InitPieCtrl();
IER = 0X0000;
IFR = 0X0000;
InitPieVectTable();
EALLOW;
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EPwm1Regs.TBCTL.bit.SWFSYNC = 0x1;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
IER |= M_INT3;
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
EINT;
ERTM;
for(;;)
{
asm(" NOP");
}
}
//end of main
interrupt void epwm1_isr(void)
{
EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
interrupt void epwm2_isr(void)
{
EPwm2TimerIntCount++;
EPwm2Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
interrupt void epwm3_isr(void)
{
EPwm3TimerIntCount++;
EPwm3Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = TBPEAK;
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;
EPwm1Regs.TBCTR = 0X0000;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PHSDIR = 1;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 0x1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.CMPA.bit.CMPA = COMPARE;
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;
}
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = TBPEAK;
EPwm2Regs.TBPHS.bit.TBPHS = (TBPEAK/2)/3;
EPwm2Regs.TBCTR = 0X0000;
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm2Regs.TBCTL.bit.PHSDIR = 1;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0x0;
EPwm2Regs.CMPA.bit.CMPA = COMPARE;
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
EPwm2Regs.ETSEL.bit.INTEN = 1;
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;
}
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = TBPEAK;
EPwm3Regs.TBPHS.bit.TBPHS = 2*(TBPEAK/2)/3;
EPwm3Regs.TBCTR = 0X0000;
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm3Regs.TBCTL.bit.PHSDIR = 1;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0x0;
EPwm3Regs.CMPA.bit.CMPA = COMPARE;
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
EPwm3Regs.ETSEL.bit.INTEN = 1;
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;
}THE CODE IS ATTACHED .THE FRQUENCY OF EPwm is changing with the change of COMPARE (CMPA) value.
LAUNCHXL-F28379D IS USED.
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