Hi,
We have already using DUALPORT RAM and SARAM in our boards. They are working fine via XINTF.
Now we want to use Microchip Brand Flash Ram which is SST39VF800A. All three memory must work on the board. You can see the timing configuration for all memories. I also configured the GPIOs as shown below.
However when I looked the flash memory location from Memory Browser, I see all the values of flash memory is equal to 1. I can't change the flash memory values to 0. They always stay at 1. I tried to change the values via memory browser on debug mode. Where could i be doing wrong?
void ConfigXintf(void)
{
EALLOW;
// XINTF configuration
XintfRegs.XINTCNF2.bit.XTIMCLK = 0; // XTIMCLK = SYSCLKOUT = 150MHz
XintfRegs.XINTCNF2.bit.CLKMODE = 0; // XCLKOUT = XTIMCLK = 150 MHz
XintfRegs.XINTCNF2.bit.CLKOFF = 0; // Enable XCLKOUT
XintfRegs.XINTCNF2.bit.WRBUFF = 0; // No write buffering
XintfRegs.XINTCNF2.bit.HOLD = 1; // Does not grant a request to an external device
// ZONE 0 - Timing for 4k x16 Dualport SRAM Access
XintfRegs.XTIMING0.bit.XWRLEAD = 1; // zone write timing
XintfRegs.XTIMING0.bit.XWRACTIVE = 1;
XintfRegs.XTIMING0.bit.XWRTRAIL = 0;
XintfRegs.XTIMING0.bit.XRDLEAD = 1; // zone read timing
XintfRegs.XTIMING0.bit.XRDACTIVE = 2;
XintfRegs.XTIMING0.bit.XRDTRAIL = 0;
XintfRegs.XTIMING0.bit.X2TIMING = 0; // don't double all zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.USEREADY = 0; // does not sample XREADY signal
XintfRegs.XTIMING0.bit.READYMODE = 0; // sample asynchronous
XintfRegs.XTIMING0.bit.XSIZE = 3; // configured for 16-bit mode
// ZONE 6 - Timing for 512k x16 Flash Access
XintfRegs.XTIMING6.bit.XWRLEAD = 3; // zone write timing
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
XintfRegs.XTIMING6.bit.XRDLEAD = 3; // zone read timing
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
XintfRegs.XTIMING6.bit.X2TIMING = 1; // double all zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.USEREADY = 0; // does not sample XREADY signal
XintfRegs.XTIMING6.bit.READYMODE = 0; // sample asynchronous
XintfRegs.XTIMING6.bit.XSIZE = 3; // configured for 16-bit mode
// ZONE 7 - Timing for 512k x16 SRAM Access
XintfRegs.XTIMING7.bit.XWRLEAD = 1; // zone write timing
XintfRegs.XTIMING7.bit.XWRACTIVE = 0;
XintfRegs.XTIMING7.bit.XWRTRAIL = 0;
XintfRegs.XTIMING7.bit.XRDLEAD = 1; // zone read timing
XintfRegs.XTIMING7.bit.XRDACTIVE = 1;
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
XintfRegs.XTIMING7.bit.X2TIMING = 0; // don't double all zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.USEREADY = 0; // does not sample XREADY signal
XintfRegs.XTIMING7.bit.READYMODE = 0; // sample asynchronous
XintfRegs.XTIMING7.bit.XSIZE = 3; // configured for 16-bit mode
// Bank switching
// Zone 6 is slow, so add additional BCYC cycles
// when ever switching from Zone 6 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 6;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
void InitDSPXintf16Gpio()
{
EALLOW;
/* Configure XINTF pins using GPIO regs*/
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 0; // Configure GPIO63 as GPIO63 (nSEMR for dualport memory)
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up on GPIO63 (nSEMR)
GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1; // Configure GPIO63 as Output
GpioDataRegs.GPBDAT.bit.GPIO63 = 1; // Set nSEMR
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 0; // Configure GPIO62 as GPIO62 (INTR for dualport memory)
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up on GPIO62 (INTR)
GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0; // Configure GPIO62 as Input
GpioDataRegs.GPBDAT.bit.GPIO62 = 1; // Set INTR
EDIS;
}
