TMS320F28388D: Can not use the Ethercat RAM

Simon, 

We will get back to you on this soon.

Thanks.

Simon, 

Hope you have referred to this thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/956370/tms320f28388d-problem-to-use-the-ethercat--ram

The relevant expert is on leave and will get back to you early next week.

Simon Schoch said:

In order for the program to get here at all, the following modifications had to be made:

Could you explain why these modifications have been made in this manner?

Thanks.

Hi Sahil,

Yes exactly, I am referring to the thread mentioned.

• "SysCtl_allocateSharedPeripheral(SYSCTL_PALLOCATE_ETHERCAT, 0U);" was inserted because the bit "PALLOCATE0.ETHERCAT" is otherwise set to 1 and Ethercat is thus assigned to the CM. According to the documentation "Technical Reference Manual SPRUII0D" this bit should be 0 after a reset!
  
• The test "while(ESC_loadedCheckEEPROM() != ESC_EEPROM_SUCCESS)..." was commented out, because otherwise an error always occurred. Why the error occurs is not clear, but the EEPROM must not be loaded, if only the Ethercat Ram is to be used. 

Best regards,

Simon

Simon, 

Simon Schoch said:

"SysCtl_allocateSharedPeripheral(SYSCTL_PALLOCATE_ETHERCAT, 0U);" was inserted because the bit "PALLOCATE0.ETHERCAT" is otherwise set to 1 and Ethercat is thus assigned to the CM. According to the documentation "Technical Reference Manual SPRUII0D" this bit should be 0 after a reset!

The above line is unnecessary as documented in the TRM, default access is mapped to CPU1. As you may have notice, none of the CPU1 examples have that function call. That being said, there is not a huge downside in calling that function either.

Your query has been assigned to the expert so you can expect a response soon.

Thanks.

Simon,

Can you please confirm the below:

1. What is your hardware setup? Are you using control card?

2. Have you commented anything else from the example like pinmux config or other init sequences?

The EEPROM load fail indicates one of the above step has not happened properly. 

Regards,

Praveen

Hi Praveen,

1. Yes I use the controlCARD MCU063A-.
   The designation on the processor is:
   XF28388DZWTS
   $7  92A9GVW
   -> The silicon revision is 0.
2. I have changed the example only in the mentioned items. pinmux config or other init sequences I have not changed.

I think the EEPROM does not need to be loaded, because we only want to use the Ethercat RAM as general RAM.

Best regards,

Simon

Simon,

For the CPU to access the ECAT RAM, the EEPROM load step needs to be completed. Hence I would suggest you to try to flash the EEPROM to get the EEPROM load done. You can refer to the Ethercat software user guide present in C2000ware to program the EEPROM present in the control card: <C2000ware path>\libraries\communications\Ethercat\f2838x\docs

In the meanwhile, I will try to check with internal teams to see if there are other ways around.

Regards,

Praveen

Hi Praveen,

I have now installed the TwinCAT program as it says in the manual, but when scanning the devices it does not find the controlCard. I don't want to follow up this problem now, because in our target we want to use the Ethercat RAM as general RAM and without EEPROM.
We are interested in a solution that allows access to the EtherCAT RAM with the configuration of the internal registers.

Best regards

Simon

Hi Simon,

You can also access the EtherCAT RAM via the fast port(address list section 8.3 of the userguide) without having to go through the EEROM load. Can you try through this address?

Regards,

Praveen

Hi Praveen

I cannot find the section 8.3 in the "EtherCAT Slave Controller Software USER'S GUIDE" (latest version v2.01.00.00). Where can I find the referred user's guide or the fast port address list?

Best regards

Simon

Simon,

Apologies, I should have been more explicit.

I meant in the device datasheet:

www.ti.com/.../datasheet

Regards,

Praveen

Hi Raveen

OK, in the datasheet I can find the section 8.3., but a "fast port" I cannot find there. The start address for the EtherCAT RAM is there 0x00030800: 

In the Document "Technical Reference Manual" (SPRUII0D) The start address for the EtherCAT RAM is 0x00050800:

There is a difference between this two documents. In the forum 
tms320f28388d-problem-to-use-the-ethercat--ram
the discrepancy of the addresses in the CM between the
"Technical Reference Manual" and the "Data Sheet" was answered by Christopher Chiarella. The address from the "Technical Reference Manual" seems to be correct.

In the example "f2838x_cpu1_pdi_hal_test_app" the ESC Registers Base Address is:
#define ESC_BASE 0x50000UL
So the EtherCAT RAM in CPU1 is probably at the address 0x00050800. Can you confirm this?

Best regards

Simon

Simon,

The EtherCAT RAM can be accessed via two addresses. The address listed in the TRM needs the EEPROM to be loaded and the Fast port address doesnt need the EEPROM to be loaded.  Please try accessing via the 0x00030800 address

Regards,

Praveen

Hi Praveen

Yes exactly, that is the solution, thank you.

I can write and read to the EtherCAT RAM in CPU1 at address 0x00030800 and in CM at address 0x400b1000.

Although the ENABLE_DEBUG_ACCESS bit is set in ECAT_ACCESS_CTRL, I cannot view this memory area via the debugger.

Best regards

Simon

Simon,

That might be due to the fact that CCS Gel file memory map definition is not having this memory listed and it is simply blocking it. Are you able to use this memory via direct CPU access?

Regards,

Praveen

Simon,

Yes, Zeroing the memory is not possible till we allocate the memory to CM.

Glad to hear that your requirement is taken care.

Have a good day

Regards,

Praveen