TMS320F280049C: Odd number of data bytes in hex record

Hi Phil,

I will review this and get back to you in couple of days.

Thanks and regards,

Vamsi

Hi Phil,

I assigned this to our compiler team to help you on the hex file question.  Once you close the discussion with them on whether the odd bytes is valid or not, I will clarify further on the flash programming possibility at byte level.

Thanks and regards,
Vamsi

Phil Gillaspy said:

I have a hex file with a record containing an odd number of data bytes.

Every record is a combination of bytes that describe the record, along with the bytes which are actually loaded to the target system.  My first guess is you have confused the two, and are counting something you should not.

Phil Gillaspy said:

The hex file is Intel hex format.

Please learn that format by searching the C28x assembly tools manual for the sub-chapter titled Intel MCS-86 Object Format.  Carefully consider this record again.  Do you still count an odd number of bytes?

Thanks and regards,

-George

I apologize, I should have shown the actual hex file record in order to avoid this reply.  Here are two the actual hex records:

:205A4400064839062A1FF524A9C4030102020604434242E4FF43E484060148FB48AE0148F6
:205A6400CB0648F7064804064801061F22C029681A48D82A1FF524A9C40648A50648EE069B
:0B5A840048D10648D60648F906000687   ELEVEN BYTES OF DATA
:205A90000080117F437F977F0F7FAB7F6D7F587F6D7EB07E247ECC7DAC7DC97C287CCD7B35
:205AB000BE7B027A9D799879F878C5770776C6750B74DD74477352720871736F9E6E936DE1

and here is another hex file snippet:

:2092F000D60633FC5AA611A91000001D0490A4031F749DA4A3C6D60633FC00ABFFAAFF0195
:20931000AB04000005A4C4A40248DC0604D542C5444100AD84A548D08406A6000FA620A653
:11933000000FA6A8201FF71C061FF71A06060106062E  SEVENTEEN BYTES OF DATA
:2095400056086508740883089208A008AE08BC08CA08D808E2081D0854088B08BF08F3080B
:2095600027085B088F08C108F308250857088908BB08EC081D082B08510860086F087E0814

Please post the linker map file for the build that leads to this hex file.  So that the forum accepts it, add the file extension .txt to it.

Thanks and regards,

-George

Attached is linker command file:

#ifdef RUN_FROM_BANK0
/* Linker commands to generate execution out of Bank 0 */
MEMORY
{
   PAGE 0 :

   BOOT_RSVD   : origin = 0x000002, length = 0x0000F3     /* Part of M0, BOOT rom will use this for stack */

   RAMM0       : origin = 0x0000F6, length = 0x00030A
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

   RAMLS0      : origin = 0x008000, length = 0x000800
   RAMLS1      : origin = 0x008800, length = 0x000800
   RAMLS2      : origin = 0x009000, length = 0x000800
   RAMLS3      : origin = 0x009800, length = 0x000800
   RAMLS4      : origin = 0x00A000, length = 0x000800
   RAMLS5      : origin = 0x00A800, length = 0x001800

   RAMGS0      : origin = 0x00C000, length = 0x002000
   RAMGS1      : origin = 0x00E000, length = 0x002000
   RAMGS2      : origin = 0x010000, length = 0x002000
   RAMGS3      : origin = 0x012000, length = 0x001F00

   RESET       : origin = 0x3FFFC0, length = 0x000002

   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN       : origin = 0x080000, length = 0x000002

   // BANK 0  - on chip flash
   FLASH_BANK0 : origin = 0x080002, length = 0x00EFF4

   /* BANK 1 - on chip flash */
   FLASH_BANK1 : origin = 0x090000, length = 0x00EFF8

   /* Define end of RAMGSx memory used for RAM memory test */
   RAM_TEST    : origin = 0x013F00, length = 0x100

   /* Define flash location to save CRC flash address */
   /* when running out of Bank 0 */
   CRC_BANK0   : origin = 0x8EFF6, length = 8

   /* Define flash location to save CRC flash address */
   /* when running out of Bank 1 */
   CRC_BANK1   : origin = 0x9EFF8, length = 8

} // end MEMORY


SECTIONS
{
   codestart        : > BEGIN,                PAGE = 0, ALIGN(4)
   .text            : >>FLASH_BANK0           PAGE = 0, ALIGN(4)
   .cinit           : > FLASH_BANK0,          PAGE = 0, ALIGN(4)
   .pinit           : > FLASH_BANK0,          PAGE = 0, ALIGN(4)
   .switch          : > FLASH_BANK0,          PAGE = 0, ALIGN(4)
   .reset           : > RESET,                PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM0 | RAMM1,        PAGE = 0

   .data            : > RAMLS5,               PAGE = 0
   .sysmem          : > RAMLS5,               PAGE = 0

   /* Initalized sections go in Flash */
   .econst          : > FLASH_BANK0,          PAGE = 0, ALIGN(4)
   .ebss            : > RAMLS4 | RAMLS5,      PAGE = 0
   .esysmem         : > RAMLS5,               PAGE = 0
   .cio             : > RAMM1,                PAGE = 0

   /* Allocate IQ math areas: */
   IQmath           : > RAMGS1,    PAGE = 0            /* Math Code */
   IQmathTables     : > RAMGS1,    PAGE = 0
    .TI.ramfunc : {} LOAD = FLASH_BANK0,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)

   rts_lib
   {
      --library=rts2800_fpu32.lib(.text)
   } > FLASH_BANK0

   UNION run = FLASH_BANK0, PAGE = 0
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

   /* Define section used for RAM memory test */
   ramTestSection  : > RAM_TEST, PAGE = 0

   /* Define section for storage location of CRC's address */
   crcBank0AddressSection : > CRC_BANK0, PAGE = 0, ALIGN(4)
   crcBank1AddressSection : > CRC_BANK1, PAGE = 0, ALIGN(4)

} // end SECTIONS
#endif // RUN_FROM_BANK0

#ifdef RUN_FROM_BANK1
/* Linker commands to generate execution out of Bank 1 */
MEMORY
{
   PAGE 0 :

   BOOT_RSVD   : origin = 0x000002, length = 0x0000F3     /* Part of M0, BOOT rom will use this for stack */

   RAMM0       : origin = 0x0000F6, length = 0x00030A
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */

   RAMLS0      : origin = 0x008000, length = 0x000800
   RAMLS1      : origin = 0x008800, length = 0x000800
   RAMLS2      : origin = 0x009000, length = 0x000800
   RAMLS3      : origin = 0x009800, length = 0x000800
   RAMLS4      : origin = 0x00A000, length = 0x000800
   RAMLS5      : origin = 0x00A800, length = 0x001800

   RAMGS0      : origin = 0x00C000, length = 0x002000
   RAMGS1      : origin = 0x00E000, length = 0x002000
   RAMGS2      : origin = 0x010000, length = 0x002000
   RAMGS3      : origin = 0x012000, length = 0x001F00

   RESET       : origin = 0x3FFFC0, length = 0x000002

   /* BEGIN is used for the "boot to Flash" bootloader mode   */
   BEGIN       : origin = 0x080000, length = 0x000002

   // BANK 0  - on chip flash
   FLASH_BANK0 : origin = 0x080002, length = 0x00EFF4

   /* BANK 1 - on chip flash */
   FLASH_BANK1 : origin = 0x090000, length = 0x00EFF8

   /* Define end of RAMGSx memory used for RAM memory test */
   RAM_TEST    : origin = 0x013F00, length = 0x100

   /* Define flash location to save CRC flash address */
   /* when running out of Bank 0 */
   CRC_BANK0   : origin = 0x8EFF6, length = 8

   /* Define flash location to save CRC flash address */
   /* when running out of Bank 1 */
   CRC_BANK1   : origin = 0x9EFF8, length = 8

} // end MEMORY


SECTIONS
{
   codestart        : > BEGIN,                PAGE = 0, ALIGN(4)
   .text            : >>FLASH_BANK1           PAGE = 0, ALIGN(4)
   .cinit           : > FLASH_BANK1,          PAGE = 0, ALIGN(4)
   .pinit           : > FLASH_BANK1,          PAGE = 0, ALIGN(4)
   .switch          : > FLASH_BANK1,          PAGE = 0, ALIGN(4)
   .reset           : > RESET,                PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM0 | RAMM1,        PAGE = 0

   .data            : > RAMLS5,               PAGE = 0
   .sysmem          : > RAMLS5,               PAGE = 0

   /* Initalized sections go in Flash */
   .econst          : > FLASH_BANK1,          PAGE = 0, ALIGN(4)
   .ebss            : > RAMLS4 | RAMLS5,      PAGE = 0
   .esysmem         : > RAMLS5,               PAGE = 0
   .cio             : > RAMM1,                PAGE = 0

   /* Allocate IQ math areas: */
   IQmath           : > RAMGS1,    PAGE = 0            /* Math Code */
   IQmathTables     : > RAMGS1,    PAGE = 0
    .TI.ramfunc : {} LOAD = FLASH_BANK1,
                         RUN = RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMLS5 | RAMGS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)

   rts_lib
   {
      --library=rts2800_fpu32.lib(.text)
   } > FLASH_BANK1

   UNION run = FLASH_BANK1, PAGE = 0
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

   /* Define section used for RAM memory test */
   ramTestSection  : > RAM_TEST, PAGE = 0

   /* Define section for storage location of CRC's address */
   crcBank0AddressSection : > CRC_BANK0, PAGE = 0, ALIGN(4)
   crcBank1AddressSection : > CRC_BANK1, PAGE = 0, ALIGN(4)

} // end SECTIONS
#endif // RUN_FROM_BANK1

/*
//===========================================================================
// End of file.
//===========================================================================
*/

I have looked at several hex files now and it appears that all of the records with an odd number of bytes are associated with the last word and odd byte as:

last word = 0106

odd byte = 06

as in this hex record.

:11933000000FA6A8201FF71C061FF71A06060106062E