Other Parts Discussed in Thread: C2000WARE,
Hello,
I am trying to use the CLA on a TMS320F280049C processor and am running into some problems. I have created a simple CLA task that sets the value of a variable; however, I can't get it to work: the CLA task either never finishes, or I get a memory access error. I believe that this is something that could be fixed in the linker file, but I am unfamiliar with the linker file and how to debug problems with it. I am using the example linker file C2000Ware_4_02_00_00\device_support\f28004x\common\cmd\28004x_cla_flash_lnk.cmd. Our CPU program is fairly large, taking up four flash blocks, so I modified the .text section of the linker file to span four flash blocks instead of 1. That is the only change I made, but I still can't run the CLA with this linker configuration.
Linker file:
MEMORY{PAGE 0 : /* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002 RAMM0 : origin = 0x0000F6, length = 0x00030A
RAMLS0 : origin = 0x008000, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800 RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */ /* BANK 0 */ FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */ FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */ FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */
/* BANK 1 */ FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */ FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */ RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMLS1 : origin = 0x008800, length = 0x000800 RAMLS2 : origin = 0x009000, length = 0x000800 RAMLS5 : origin = 0x00A800, length = 0x000800 RAMLS6 : origin = 0x00B000, length = 0x000800 RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x002000 RAMGS1 : origin = 0x00E000, length = 0x002000 RAMGS2 : origin = 0x010000, length = 0x002000 RAMGS3 : origin = 0x012000, length = 0x001FF8// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080 CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080}
SECTIONS{ .cinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .text : >>FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7 | FLASH_BANK0_SEC8, PAGE = 0, ALIGN(4) codestart : > BEGIN PAGE = 0, ALIGN(4)
.stack : > RAMM1 PAGE = 1 .switch : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__) .init_array : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .bss : > RAMLS5, PAGE = 1 .bss:output : > RAMLS5, PAGE = 1 .bss:cio : > RAMLS5, PAGE = 1 .data : > RAMLS6, PAGE = 1 .sysmem : > RAMLS6, PAGE = 1 .const : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)#else .pinit : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4) .ebss : >>RAMLS5 | RAMLS6, PAGE = 1 .esysmem : > RAMLS6, PAGE = 1 .cio : > RAMLS5, PAGE = 1 .econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)#endif
ramgs0 : > RAMGS0, PAGE = 1 ramgs1 : > RAMGS1, PAGE = 1 .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
dclfuncs : > FLASH_BANK0_SEC1, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__) /* CLA specific sections */ Cla1Prog : LOAD = FLASH_BANK0_SEC4, RUN = RAMLS0, LOAD_START(Cla1ProgLoadStart), RUN_START(Cla1ProgRunStart), LOAD_SIZE(Cla1ProgLoadSize), PAGE = 0, ALIGN(4)#else /* CLA specific sections */ Cla1Prog : LOAD = FLASH_BANK0_SEC4, RUN = RAMLS0, LOAD_START(_Cla1ProgLoadStart), RUN_START(_Cla1ProgRunStart), LOAD_SIZE(_Cla1ProgLoadSize), PAGE = 0, ALIGN(4)#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1 CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#if defined(__TI_EABI__) .TI.ramfunc : LOAD = FLASH_BANK0_SEC1, RUN = RAMLS4 LOAD_START(RamfuncsLoadStart), LOAD_SIZE(RamfuncsLoadSize), LOAD_END(RamfuncsLoadEnd), RUN_START(RamfuncsRunStart), RUN_SIZE(RamfuncsRunSize), RUN_END(RamfuncsRunEnd), PAGE = 0, ALIGN(4)#else GROUP : LOAD = FLASH_BANK0_SEC1, RUN = RAMLS4 LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0, ALIGN(4) { .TI.ramfunc ramfuncs }#endif
.scratchpad : > RAMLS1, PAGE = 1 .bss_cla : > RAMLS1, PAGE = 1
Cla1DataRam : > RAMLS2, PAGE = 1 cla_shared : > RAMLS1, PAGE = 1 CLADataLS1 : > RAMLS1, PAGE = 1
#if defined(__TI_EABI__) .const_cla : LOAD = FLASH_BANK0_SEC2, RUN = RAMLS3, RUN_START(Cla1ConstRunStart), LOAD_START(Cla1ConstLoadStart), LOAD_SIZE(Cla1ConstLoadSize), PAGE = 0, ALIGN(4)#else .const_cla : LOAD = FLASH_BANK0_SEC2, RUN = RAMLS3, RUN_START(_Cla1ConstRunStart), LOAD_START(_Cla1ConstLoadStart), LOAD_SIZE(_Cla1ConstLoadSize), PAGE = 0, ALIGN(4)#endif}
/*//===========================================================================// End of file.//===========================================================================*/
CLA initialization code:
Interrupt_disableMaster();
#ifdef FLASH memcpy(&Cla1ProgRunStart, &Cla1ProgLoadStart, (uint32_t)&Cla1ProgLoadSize);#endif
// Configure CLA memory sections MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LSX_ALL, MEMCFG_LSRAMMASTER_CPU_CLA1);
MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_DATA); MemCfg_setCLAMemType(MEMCFG_SECT_LS2, MEMCFG_CLA_MEM_DATA);
// Assign task functions and set triggers #pragma diag_suppress=770 CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_1, (uint16_t) &Cla1Task1); CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_SOFTWARE); #pragma diag_warning=770
// Eanble tasks CLA_enableTasks(CLA1_BASE, CLA_TASKFLAG_1); CLA_enableIACK(CLA1_BASE); // software forcing
// Register end-of-task interrupts Interrupt_register(INT_CLA1_1, cla1Isr1);
// Enable the end-of-task interrupts in the PIE: Group 11 interrupt 1. Interrupt_enable(INT_CLA1_1); Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP11);
Interrupt_enableMaster();
CLA Task:
interrupt void Cla1Task1(void){ CLA_flag = 17;
}
Calling CLA Task:
CLA_forceTasks(CLA1_BASE, CLA_TASKFLAG_1);
