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TMDSCNCD28379D: ADC Count Fluctuation

Vishal D
Prodigy 70 points
Part Number: TMDSCNCD28379D


Hello, I am reading ADC-C5 input value which is triggered by EPWM event when count reaches to zero and reading the ADC count value when EPWM timer counter is equal to period. The EPWM period is 25 micro secs. The ADC input is driven by TI OP-AMP - OPA2834IDGKR with low pass filter resistor 220 ohm and 110PF capacitor. The values of Low pass filter is calculated using TI's Analog Engineers Calculator and finalized after simulating the ADC Driver and ADC model in a simulator with 0.5LSB error.

When I am reading the ADC value its is constantly fluctuating for constant DC voltage(from battery) as input to ADC Driver circuit. The ADC values typically fluctuate with difference of around 50 to 60. I have tried with different value of Sample Window counts (10 to 500) but not measure change in the fluctuations.

Can you please suggest how can I get a stable ADC count as I have tried most of the recommendations for the stable ADC input ?

Thanks!

  • 0
    TI__Mastermind 30185 points

    Hello Vishal,

    Is this ADC the 12-bit or 16-bit mode? Also, with the data you recorded is it possible to perform an FFT on the data to see what frequency the oscillation exists at?

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    Prodigy 70 points

    Hello Amir, The ADC is in 12 bit mode. I'll perform the FFT and share you the results shortly.

  • 0 in reply to Vishal D
    Prodigy 70 points

    Hello Amir,

    Refer attached FFT data calculated using excel add-ins. For this data captured the ADC Prescaler is selected for 8.5 clock divider and Sample window time of 500 SYSCLK(2500 nsecs). The SYSTEM Clock frequency is at 200 MHz. The input voltage to the ADC is from constant battery supply.

    FFT_Calculator.xlsx

  • 0 in reply to Vishal D
    TI__Mastermind 30185 points

    Hello Vishal,

    Your ADC values are deviating significantly, as you stated. Have you made sure to allow enough sampling time accounting for the filter impedance in your sample and hold value calculation? You can refer to the ADC Timing Diagrams section of the technical reference manual for more detail on this (section 11.14.1).

    From your description of the op amp you use on the input, I assume you have been designing to reduce noise from the supplied DC value. Have you checked to see if the signal source is noisy at all?

    Additionally, are there any GPIO toggling or other sorts of oscillations happening? This can cause deviation on analog pins if happening frequently.

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    Prodigy 70 points

    Hello Amir,

    Thank you for the suggestions.

    The Sample and Hold timing as per the filter components appears to be around 230nsecs and the S/H window I kept is around 2500 nsec which is far more than expected. I have also verified that the ADC result is read almost 20 micro secs later after the conversion is completed.

    The input voltage source is from 12V/7AH battery which is not noisy source.

    The ADC driving model which I have used for Driving ADC is as per TI's precision lab series: https://training.ti.com/node/1139106

    I have tried to change the ADC input far away from the EPWM pins which are the only toggling ports in my design but got the same results with this change.

  • 0 in reply to Vishal D
    TI__Mastermind 30185 points

    Hello Vishal,

    Vishal D said:
    The Sample and Hold timing as per the filter components appears to be around 230nsecs and the S/H window I kept is around 2500 nsec which is far more than expected. I have also verified that the ADC result is read almost 20 micro secs later after the conversion is completed.

    Can you tell me what ACQPS value you are using in the ADC SOC configuration?

    And just to double-check, can you scope the input into the ADC to see what the DC signal looks like?

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    TI__Mastermind 30185 points

    As an additional check, what is the ADC clock configuration you have set? The ADC clock should be between 5 and 50 MHz.

  • 0 in reply to Omer Amir
    Prodigy 70 points

    Hello Amir,

    Thank you for the suggestions, I checked the ADC clock it is SYSCLK(200MHz)/ADCCLK_DIV(4) = 50MHz. I checked the power supply which is given to board where it has ripples of around 40 to 60 mV which might be causing the issue. So I will try on another more stable power supply and let you know if the issue persist. Till the time you can close the this issue.