TMS320F28379D: EMIF interfacing with FM22L16 F-RAM

sonam singh said:

I've been working on my customized board using example code to access EMIF for FM22L16 (18 address lines & 16 data lines) .

Would you be willing to share the schematics of your board privately? You can do this by initiating a friendship request with me. You will tehn be able to send private messages which will not be visible on the forum.

sonam singh said:

I can perform the reading  and writing on the same FM22L16 by using GPIO.

You achieved successful R/W operations by bit-banging the FRAM chip with GPIO pins?!

sonam singh said:

I'm able to perform the write operation but can't access the reading.

How did you ascertain successful writes when you are unable to read?

sonam singh said:

I couldn't access the dedicated address assign for cs2 pin which is 0x0010 0000 I'm unable to perform read operation on this specific address.

Is the CS2 pin going low at all? One area to check would be whether the read access timings are compatible with the FRAM chip.

yes sir and using the same GPIO compatible with EMIF address pins and EMIF data pins by using bit banging.By observing the WE pins on DSO. Also examined the signal on address and data pins of FM22L16 over DSO. 

Hareesh Janakiraman said:

You achieved successful R/W operations by bit-banging the FRAM chip with GPIO pins?!

Hareesh Janakiraman said:

low

The CS2 pin goes low for 100 ns. I use the both configuration 50 ns & 100ns by using function [ SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);]

Hareesh Janakiraman said:

whether

Could you please guide me how to check the  read access time compatibility with the FRAM chip.

sonam singh said:

Could you please guide me how to check the  read access time compatibility with the FRAM chip.

The access time information should be available in the datasheet of the FRAM chip.

Hareesh Janakiraman said:

The access time information should be available in the datasheet of the FRAM chip.

It appears the access time is 110 ns, from the datasheet.

sonam singh said:

The CS2 pin goes low for 100 ns.

If CS2 goes low, that means the address is decoded correctly by the EMIF. Please re-check your timing configuration.

You have not answered the following questions: 

1. Would you be willing to share the schematics of your board privately? 
2. How did you ascertain successful writes when you are unable to read?

Hareesh Janakiraman said:

Would you be willing to share the schematics of your board privately? 

I'll provide you the schematics by tomorrow morning.

Hareesh Janakiraman said:

How did you ascertain successful writes when you are unable to read?

I observed the signal over DSO the WE pin gets HIGH, can observe the signal changes for address line and data lines signal changes by writing the code in a while loop.

These changes in for address and data lines signal are not present while read operation.

Sonam,

          I will take a look at the schematics but I am afraid our ability to help with an issue like this is very limited. www.ti.com/lit/SPRAC96 is a good resource that explains the interfacing of asynch memory to EMIF. C2000ware examples show how to configure the module for operation. Going beyond this would involve a deep dive into the characteristics of FM22L16, which we are not equipped to do.

Hareesh Janakiraman said:

   I will take a look at the schematics but I am afraid our ability to help with an issue like this is very limited. www.ti.com/lit/SPRAC96 is a good resource that explains the interfacing of asynch memory to EMIF. C2000ware examples show how to configure the module for operation. Going beyond this would involve a deep dive into the characteristics of FM22L16, which we are not equipped to do.

SCHEMATIC1 _ PAGE1.pdf

Please find the schematic for reference. I'm sharing the modified code I've been using for writing and reading...

//#############################################################################
//
// FILE: emif_ex1_16bit_asram.c
//
// TITLE: EMIF1 ASYNC module accessing 16bit ASRAM.
//
//! \addtogroup driver_example_list
//! <h1> EMIF1 ASYNC module accessing 16bit ASRAM. </h1>
//!
//! This example configures EMIF1 in 16bit ASYNC mode and uses CS2 as chip
//! enable.
//!
//! \b External \b Connections \n
//! - External ASRAM memory (CY7C1041CV33 -10ZSXA) daughter card
//!
//! \b Watch \b Variables \n
//! - \b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter
//!
//
//#############################################################################
// $TI Release: F2837xD Support Library v3.08.00.00 $
// $Release Date: Mon Dec 23 17:32:30 IST 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################

//
// Included Files
//
#include "device.h"
#include "driverlib.h"

//
// Defines
//
#define TEST_PASS 0xABCDABCD
#define TEST_FAIL 0xDEADDEAD
#define ASRAM_CS2_START_ADDR 0x00100000
#define end_address 0x0010FDE8
#define ASRAM_CS2_SIZE 0x8000

//
// Globals
//
uint16_t errCountGlobal = 0;
uint32_t testStatusGlobal;
uint32_t i;

//
// Function Prototypes
//
extern void setupEMIF1PinmuxAsync16Bit(void);
uint16_t readWriteMem(uint32_t startAddr, uint32_t memSize);
uint16_t walkMemData(uint32_t startAddr, uint32_t memSize);
uint16_t walkMemAddr(uint32_t startAddr, uint32_t addrSize);
uint16_t accessMemData(uint32_t startAddr, uint32_t sizeToCheck);

//
// Main
//
void main(void)
{
uint16_t errCountLocal;
EMIF_AsyncTimingParams tparam;
testStatusGlobal = TEST_FAIL;

//
// Initialize device clock and peripherals.
//
Device_init();

//
// Disable all the interrupts.
//
DINT;

//
// Setup GPIO by disabling pin locks and enabling pullups.
//
Device_initGPIO();

//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();

//
// Configure to run EMIF1 on full Rate. (EMIF1CLK = CPU1SYSCLK)
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);

//
// Grab EMIF1 For CPU1.
//
EMIF_selectMaster(EMIF1CONFIG_BASE, EMIF_MASTER_CPU1_G);

//
// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);

//
// Commit the configuration related to protection. Till this bit remains
// set, contents of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);

//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);

//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxAsync16Bit();

//
// Configures Normal Asynchronous Mode of Operation.
//
EMIF_setAsyncMode(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_NORMAL_MODE);

//
// Disables Extended Wait Mode.
//
EMIF_disableAsyncExtendedWait(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET);

//
// Configure EMIF1 Data Bus Width.
//
EMIF_setAsyncDataBusWidth(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_DATA_WIDTH_16);

//
// Configure the access timing for CS2 space.
//
tparam.rSetup = 0;
tparam.rStrobe = 3;
tparam.rHold = 0;
tparam.turnArnd = 0;
tparam.wSetup = 0;
tparam.wStrobe = 1;
tparam.wHold = 0;
EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tparam);
while(1)
{
//
// Checks basic RD/WR access to CS2 space.
//
errCountLocal = readWriteMem(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;
}
//
// Address walk checks. (Tested for Memory with address width of 16bit)
//
errCountLocal = walkMemAddr(ASRAM_CS2_START_ADDR, 16);
errCountGlobal = errCountGlobal + errCountLocal;
//}
//
// Data walk checks.
//
errCountLocal = walkMemData(ASRAM_CS2_START_ADDR, ASRAM_CS2_SIZE);
errCountGlobal = errCountGlobal + errCountLocal;

//
// Data size checks.
//
errCountLocal = accessMemData(ASRAM_CS2_START_ADDR, 4);
errCountGlobal = errCountGlobal + errCountLocal;

if(errCountGlobal == 0x0)
{
testStatusGlobal = TEST_PASS;
}

}

// 0x0000041E
// Read Write Memory - This function performs simple read/write word accesses
// to memory.
//
uint16_t readWriteMem(uint32_t startAddr, uint32_t memSize)
{
uint32_t memReadData;
uint32_t memWriteData=0;
uint32_t *memPtr;
uint32_t i;

memPtr = (uint32_t *)startAddr;

// Write data to memory.

// while(1)
// {
// for(i = 0; i < 65000; i++)
// {
// memWriteData = i;
// *memPtr++ = memWriteData;

// if( *memPtr++>=end_address)memPtr = (uint32_t *)startAddr;
// }
// }
// Verify data written to memory.


memPtr = (uint32_t *)startAddr;
while(1)
{
for(i = 0; i < 65000; i++)
{
memReadData = *memPtr;

memPtr++;
if( *memPtr++>=end_address)memPtr = (uint32_t *)startAddr;


}
}
// return(0);
}

//
// Walk Memory Data - This function performs a walking 0 & 1 on data lines
// for SRAM RD & WR.
//
uint16_t walkMemData(uint32_t startAddr, uint32_t memSize)
{
uint32_t sramReadData;
uint32_t sramWriteData;
uint32_t i;
uint32_t k;
uint32_t m;
uint32_t *memPtr;
uint32_t *memPtrIter;

memPtr = (uint32_t *)startAddr;

for(i = 0; i < memSize; i = i + 64)
{
for(m = 0; m < 2; m++)
{
//
// Write loop.
//
memPtrIter = memPtr;
sramWriteData = 0x01;
for(k = 0; k < 32; k++)
{
if(m == 0)
{
*memPtrIter++ = sramWriteData;
}
else
{
*memPtrIter++ = ~sramWriteData;
}
sramWriteData = sramWriteData << 1;
}

//
// Read loop.
//
memPtrIter = memPtr;
sramWriteData = 0x01;
for(k = 0; k < 32; k++)
{
sramReadData = *memPtrIter;
if(m == 1)
{
sramReadData = ~sramReadData;
}
if(sramReadData != sramWriteData)
{
return(1);
}
memPtrIter++;
sramWriteData = sramWriteData << 1;
}
}
memPtr = memPtrIter;
}
return(0);
}

//
// Walk Memory Addresses - This function performs a toggle on each address bit.
//
uint16_t walkMemAddr(uint32_t startAddr, uint32_t addrSize)
{
uint32_t sramReadData;
uint32_t sramWriteData;
uint32_t k;
uint32_t xshift;
uint32_t *memPtr;
uint32_t *memPtrIter;

memPtr = (uint32_t *)startAddr;

//
// Write loop.
//
xshift = 0x00000001;
sramWriteData = 0x00;
for(k = 0; k < addrSize; k++)
{
memPtrIter = (uint32_t *)(startAddr + xshift);
*memPtrIter = sramWriteData++;
xshift = xshift << 1;
}

//
// Read loop.
//
memPtrIter = memPtr;
xshift = 0x00000001;
sramWriteData = 0x00;
for(k = 0; k < addrSize; k++)
{
memPtrIter = (uint32_t *)(startAddr + xshift);
sramReadData = *memPtrIter;
if(sramReadData != sramWriteData)
{
return(1);
}
xshift = xshift << 1;
sramWriteData++;
}
return(0);
}

//
// Access Memory Data - This function performs different data type
// (HALFWORD/WORD) access.
//
uint16_t accessMemData(uint32_t startAddr, uint32_t sizeToCheck)
{
uint16_t memRdShort;
uint32_t memRdLong;
uint16_t memWrShort;
uint32_t memWrLong;
uint32_t i;
uint16_t *memPtrShort;
uint32_t *memPtrLong;

//
// Write short data.
//
memPtrShort = (uint16_t *)startAddr;
memWrShort = 0x0605;

for(i = 0; i < 2; i++)
{
*memPtrShort++ = memWrShort;
memWrShort += 0x0202;
}

//
// Write long data.
//
memPtrLong = (uint32_t *)memPtrShort;
memWrLong = 0x0C0B0A09;
for(i = 0; i < 2; i++)
{
*memPtrLong++ = memWrLong;
memWrLong += 0x04040404;
}

//
// Read short data.
//
memPtrShort = (uint16_t *)startAddr;
memWrShort = 0x0605;
for(i = 0; i < 6; i++)
{
memRdShort = *memPtrShort;
if(memRdShort != memWrShort)
{
return(1);
}
memPtrShort++;
memWrShort += 0x0202;
}

//
// Read long data.
//
memPtrLong = (uint32_t *)startAddr;
memWrLong = 0x08070605;
for(i = 0; i < 3; i++)
{
memRdLong = *memPtrLong;
if(memRdLong != memWrLong)
{
return(1);
}
memPtrLong++;
memWrLong += 0x04040404;
}
return(0);
}

//
// End of File
//

While reading the signal on address pin signals are available but the data line signals are permanently LOW.

Sonam,

              The connections appear to be fairly straightforward, similar to F28379D_EMIF_DC_SCH.pdf in C:\ti\c2000\C2000Ware_4_02_00_00\boards\TIDesigns\F28379D_EMIF_DC. 

Debugging your code is not something we can support on e2e. The C2000ware example is a tested example. If it doesn't work, there likely is an issue with the timing configuration for the FRAM chip. Please ensure you are meeting the timing requirements for the FRAM chip.

sonam singh said:

While reading the signal on address pin signals are available but the data line signals are permanently LOW.

This likely indicates a possible config issue with the FRAM chip. Please reach out to the FRAM chip manufacturer for support.