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TMS320F280039C: Flash programming via SCI on custom boards

Conor
Guru 13015 points
Part Number: TMS320F280039C


Hi, 

Using a custom board, the application program is written from GPIO8 and GPIO9 via SCI. I was able to expand the kernel software to RAM, but it stopped in the following state while transferring the application code.


I tried 19200bps and 9600bps baud rate, but it stops at the same point. At that time, on the CCS screen, a part of the CLA interrupt processing breaks and stops.

The kernel may be misconfigured because it hangs when transferring the application program.

By the way, I succeeded in transferring the txt file of the same kernel and application code using the evaluation board. Our application code uses CLA. The linker command file is also attached just in case. The CLA program is expanded to RAM in the linker command file. Will this have any impact?

Fullscreen F280039_flash_lnk .txt Download 
/*
//###########################################################################
//
// FILE:	F280039_flash_lnk.cmd
//
// TITLE:	Linker Command File For F280039 Device
//
//###########################################################################
*/
MEMORY
{

   BOOT_RSVD		: origin = 0x00000002, length = 0x00000126

   RAMM0           	: origin = 0x00000128, length = 0x000002D8
   RAMM1            : origin = 0x00000400, length = 0x000003F8     /* on-chip RAM block M1 */
// RAMM1_RSVD       : origin = 0x000007F8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

//   RAMLS0           : origin = 0x00008000, length = 0x00000800
//   RAMLS1           : origin = 0x00008800, length = 0x00000800
   RAMLS0_2         : origin = 0x00008000, length = 0x00001800
//   RAMLS2           : origin = 0x00009000, length = 0x00000800
   RAMLS3           : origin = 0x00009800, length = 0x00000800
   RAMLS4           : origin = 0x0000A000, length = 0x00000800
   //RAMLS5           : origin = 0x0000A800, length = 0x00000800
   //RAMLS6           : origin = 0x0000B000, length = 0x00000800
   RAMLS_5_6		:origin = 0x0000A800,length = 0x00001000
   RAMLS7           : origin = 0x0000B800, length = 0x00000800

   /* Combining all the LS RAMs */
   //RAMLS            : origin = 0x00008000, length = 0x00004000
   
   RAMGS0           : origin = 0x0000C000, length = 0x00001000
   RAMGS1           : origin = 0x0000D000, length = 0x00001000
   RAMGS2           : origin = 0x0000E000, length = 0x00001000
   RAMGS3           : origin = 0x0000F000, length = 0x00000FF8
// RAMGS3_RSVD       : origin = 0x000FFF8, length = 0x00000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   BOOTROM          : origin = 0x003F8000, length = 0x00007FC0
   SECURE_ROM       : origin = 0x003F2000, length = 0x00006000

   RESET            : origin = 0x003FFFC0, length = 0x00000002

   CLA1_MSGRAMLOW   : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH  : origin = 0x001500, length = 0x000080


#ifdef __TI_COMPILER_VERSION__
   #if __TI_COMPILER_VERSION__ >= 20012000
GROUP {      /* GROUP memory ranges for crc/checksum of entire flash */
   #endif
#endif
   BEGIN           	: origin = 0x00080000, length = 0x00000002
   /* Flash sectors */
   /* BANK 0 */
   FLASH_BANK0_SEC0  : origin = 0x080002, length = 0x000FFE
   FLASH_BANK0_SEC1  : origin = 0x081000, length = 0x001000
   FLASH_BANK0_SEC2  : origin = 0x082000, length = 0x001000
   FLASH_BANK0_SEC3  : origin = 0x083000, length = 0x001000
   FLASH_BANK0_SEC4  : origin = 0x084000, length = 0x001000
   FLASH_BANK0_SEC5  : origin = 0x085000, length = 0x001000
   FLASH_BANK0_SEC6  : origin = 0x086000, length = 0x001000
   FLASH_BANK0_SEC7  : origin = 0x087000, length = 0x001000
   //FLASH_BANK0_SEC8  : origin = 0x088000, length = 0x001000
   //FLASH_BANK0_SEC9  : origin = 0x089000, length = 0x001000
   FLASH_BANK0_SEC8_9  : origin = 0x088000, length = 0x002000	/* on-chip Flash */
   FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000
   FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000
   FLASH_BANK0_SEC12_13 : origin = 0x08C000, length = 0x002000
   // FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000
   // FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000
   FLASH_BANK0_SEC14_15 : origin = 0x08E000, length = 0x001FF0
   //FLASH_BANK0_SEC14_15 : origin = 0x08E000, length = 0x002000
   //FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000
   SW_PROGRAM_VER    : origin = 0x0008FFF0, length = 0x00000010 


   /* BANK 1 */
   FLASH_BANK1_SEC0  : origin = 0x090000, length = 0x001000
   FLASH_BANK1_SEC1  : origin = 0x091000, length = 0x001000
   FLASH_BANK1_SEC2  : origin = 0x092000, length = 0x001000
   FLASH_BANK1_SEC3  : origin = 0x093000, length = 0x001000
   FLASH_BANK1_SEC4  : origin = 0x094000, length = 0x001000
   FLASH_BANK1_SEC5  : origin = 0x095000, length = 0x001000
   FLASH_BANK1_SEC6  : origin = 0x096000, length = 0x001000
   FLASH_BANK1_SEC7  : origin = 0x097000, length = 0x001000
   FLASH_BANK1_SEC8  : origin = 0x098000, length = 0x001000
   FLASH_BANK1_SEC9  : origin = 0x099000, length = 0x001000
   FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000
   FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000
   FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000
   FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000
   FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000
   FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x001000

  /* BANK 2 */
   FLASH_BANK2_SEC0  : origin = 0x0A0000, length = 0x001000
   FLASH_BANK2_SEC1  : origin = 0x0A1000, length = 0x001000
   FLASH_BANK2_SEC2  : origin = 0x0A2000, length = 0x001000
   FLASH_BANK2_SEC3  : origin = 0x0A3000, length = 0x001000
   FLASH_BANK2_SEC4  : origin = 0x0A4000, length = 0x001000
   FLASH_BANK2_SEC5  : origin = 0x0A5000, length = 0x001000
   FLASH_BANK2_SEC6  : origin = 0x0A6000, length = 0x001000
   FLASH_BANK2_SEC7  : origin = 0x0A7000, length = 0x001000
   FLASH_BANK2_SEC8  : origin = 0x0A8000, length = 0x001000
   FLASH_BANK2_SEC9  : origin = 0x0A9000, length = 0x001000
   FLASH_BANK2_SEC10 : origin = 0x0AA000, length = 0x001000
   FLASH_BANK2_SEC11 : origin = 0x0AB000, length = 0x001000
   FLASH_BANK2_SEC12 : origin = 0x0AC000, length = 0x001000
   FLASH_BANK2_SEC13 : origin = 0x0AD000, length = 0x001000
   FLASH_BANK2_SEC14 : origin = 0x0AE000, length = 0x001000
   FLASH_BANK2_SEC15 : origin = 0x0AF000, length = 0x000FF0
   FLASH_BANK2_SEC15_DO_NOT_USE : origin = 0x0AFFF0, length = 0x000010  /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
#ifdef __TI_COMPILER_VERSION__
  #if __TI_COMPILER_VERSION__ >= 20012000
}  crc(_ccs_flash_checksum, algorithm=C28_CHECKSUM_16)
  #endif
#endif

}


SECTIONS
{
   codestart        : > BEGIN, ALIGN(8)
   .text            : >> FLASH_BANK0_SEC2 | FLASH_BANK0_SEC3 | FLASH_BANK0_SEC4 | FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6 | FLASH_BANK0_SEC7 | FLASH_BANK0_SEC8_9 | FLASH_BANK0_SEC10 | FLASH_BANK0_SEC11, ALIGN(8)
   .cinit           : > FLASH_BANK0_SEC1,  ALIGN(8)
   .switch          : > FLASH_BANK0_SEC1,  ALIGN(8)
   .reset           : > RESET,                  TYPE = DSECT /* not used, */

   .stack           : > RAMM1

#if defined(__TI_EABI__)
   .init_array      : > FLASH_BANK0_SEC1,  ALIGN(8)
   .bss             : > RAMLS5
   .bss:output      : > RAMLS3
   .bss:cio         : > RAMLS0
   .data            : > RAMLS5
   .sysmem          : > RAMLS5
   .const           : > FLASH_BANK0_SEC4,  ALIGN(8)
#else
   .pinit           : > FLASH_BANK0_SEC1,  ALIGN(8)
   .ebss            : > RAMLS_5_6
   .esysmem         : > RAMLS7
   .cio             : > RAMLS7
   .econst          : > FLASH_BANK0_SEC14_15,  ALIGN(8)
   swversion        : > SW_PROGRAM_VER, ALIGN(8)
#endif

    ramgs0 : > RAMGS0
    ramgs1 : > RAMGS0
	.reset           : > RESET,TYPE = DSECT /* not used, */

    /*  Allocate IQ math areas: */
   IQmath           : > FLASH_BANK0_SEC1, ALIGN(8)
   IQmathTables     : > FLASH_BANK0_SEC2, ALIGN(8)

	/* CLA specific sections */
    Cla1Prog        : LOAD = FLASH_BANK0_SEC12_13,
                      RUN = RAMLS0_2,
                      LOAD_START(_Cla1ProgLoadStart),
                      RUN_START(_Cla1ProgRunStart),
                      LOAD_SIZE(_Cla1ProgLoadSize),
                      ALIGN(8)
   
    Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW
    CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH
    
  .TI.ramfunc      : LOAD = FLASH_BANK0_SEC1,
                      RUN = RAMLS4
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      ALIGN(8)

   .scratchpad      : > RAMLS3
   .bss_cla         : > RAMLS3

   Cla1DataRam      : > RAMLS4
   cla_shared       : > RAMLS3
   CLADataLS1       : > RAMLS3
   
   /* crc/checksum section configured as COPY section to avoid including in executable */
   .TI.memcrc          : type = COPY
   
    .const_cla      : LOAD = FLASH_BANK0_SEC2,
                      RUN = RAMLS4,
                      RUN_START(_Cla1ConstRunStart),
                      LOAD_START(_Cla1ConstLoadStart),
                      LOAD_SIZE(_Cla1ConstLoadSize),
                      ALIGN(8)
     /* CLAmathライブラリ配置セクション */
     CLA1mathTables : LOAD = FLASH_BANK0_SEC3,
                      RUN = RAMLS4,
                      RUN_START(_Cla1mathTablesRunStart),
                      LOAD_START(_Cla1mathTablesLoadStart),
                      LOAD_SIZE(_Cla1mathTablesLoadSize),
                      ALIGN(8)

}
/*
//###########################################################################
// End of file.
//###########################################################################
*/

We will change the extension of the linker command file to txt and send it to you.

Can you give me some advice?

Thanks,

Eevee

  • 0
    TI__Genius 15080 points

    Hi Eevee,

    Thanks for your question. Will get back to you within the next day.

    Thanks and regards,

    Charles

  • 0 in reply to Charles Roberson
    Guru 13015 points

    Hi, Charles

    I would greatly appreciate it if you could reply as soon as possible.

    Thanks,

    Eevee

  • 0 in reply to Conor
    TI__Genius 15080 points

    Hi Eevee,

    When you say "transferring the txt file of the same kernel and application code using the evaluation board", you mean by using the command prompt correct?

    So you are able to get past the download of the kernel, but when performing the DFU CPU1 command got the image it gets stuck?

    Also, have you tried to send the file to the device with CCS closed?

    Thanks,

    Charles

  • 0 in reply to Charles Roberson
    Guru 13015 points

    Hi, Charles

    Charles Roberson said:
    When you say "transferring the txt file of the same kernel and application code using the evaluation board", you mean by using the command prompt correct?

    With no differences other than the evaluation board and the custom board (the kernel and application code are the same), I wrote via the command prompt. As a result, this phenomenon did not occur on the evaluation board, but only on the custom board.

    Charles Roberson said:
    So you are able to get past the download of the kernel, but when performing the DFU CPU1 command got the image it gets stuck?

    Since it stops before the DFU CPU1 command selection screen is displayed, it seems that the DFU CPU1 command has not been executed. My guess is that the baud rate is adjusted before the DFU CPU1 command, and the program stops here. Please let me know if you find out what the cause is.

    The CLA program is expanded into RAM in the linker script file, does this have any effect?

    Charles Roberson said:
    have you tried to send the file to the device with CCS closed?

    Even if CCS is closed, the communication will stop in the middle and the same phenomenon will occur.

    Thanks,

    Eevee

  • 0 in reply to Conor
    TI__Genius 15080 points

    Hi Eevee,

    Have you tried to expand the CLA code to flash memory? This could be affecting it. Also, have you tried to reset the custom board before sending the kernel and application file?

    Will run some tests on the host programmer and get back to you on what I find. 

    Thanks,

    Charles

  • 0 in reply to Charles Roberson
    Guru 13015 points

    Hi, Charles

    　>Have you tried to expand the CLA code to flash memory?This could be affecting it.
    What does "expand the CLA code to flash memory" mean? I believe the CLA's code can only run in RAM because the CLA and Flash are not bused together. How exactly should I verify?

    　>Also, have you tried to reset the custom board before sending the kernel and application file?
    Even if transfer is performed after resetting, the same result is obtained. The screen freezes before the DFU CPU1 command selection screen appears. The internal clock of the microcomputer is used, and it has been confirmed that the data can be transferred normally on the evaluation board.

    We are waiting for your verification results.

    Thanks,

    Eevee

  • 0 in reply to Conor
    TI__Genius 15080 points

    Hi Eevee,

    I have noticed nothing irregular with the way the F28003 downloads the kernel file (stepping through the source with the device connected). Are you able to view the TX/RX buffers for the custom device when the transfer is occuring? If you would like to have a call over this that can be arranged. Have sent you a chat message as well.

    Thanks,

    Charles