TMS320F28374S: Creating a RAM cmd file based a FLASH cmd file

I have linker cmd file that works for flash now I want to create a cmd file that is loaded into RAM by the emulator.  Is there a reference for doing this?

My first try I get 

warning #10247-D: creating output section ".text" without a SECTIONS specification
warning #10247-D: creating output section ".data" without a SECTIONS specification
warning #10247-D: creating output section ".bss" without a SECTIONS specification
warning #10247-D: creating output section ".cinit" without a SECTIONS specification
warning #10247-D: creating output section ".const" without a SECTIONS specification
warning #10247-D: creating output section "controlVariables" without a SECTIONS specification
error #10430-D: ".TI.ramfunc" section generated by __attribute__((ramfunc)) or --ramfunc=on requires a SECTIONS specification to function.
warning #10247-D: creating output section ".DataBufferFDL" without a SECTIONS specification
warning #10247-D: creating output section "dclfuncs" without a SECTIONS specification
warning #10247-D: creating output section "codestart" without a SECTIONS specification
warning #10247-D: creating output section "SFRA_F32_Data" without a SECTIONS specification
warning #10247-D: creating output section "FPUmathTables" without a SECTIONS specification
error #10010: errors encountered during linking; "Falabella_F28379D.out" not built

From this based on 2837xS_Generic_RAM_lnk.cmd

MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */

BEGIN : origin = 0x000000, length = 0x000002
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002

PAGE 1 :

BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD1 : origin = 0x00B800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
RAMGS4 : origin = 0x010000, length = 0x001000
RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
// RAMGS10 : origin = 0x016000, length = 0x001000
// RAMGS11 : origin = 0x017000, length = 0x000FF8
// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMGS10_GS11 : origin = 0x016000, length = 0x002000
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
}

SECTIONS
{
codestart : > BEGIN, PAGE = 0
.text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMSL5, PAGE = 0
.cinit : > RAMM0, PAGE = 0
.switch : > RAMM0, PAGE = 0
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

.stack : > RAMM1, PAGE = 1

#if defined(__TI_EABI__)
.bss : > RAMGS5, PAGE = 1
.bss:output : > RAMLS5, PAGE = 0
.init_array : > RAMM0, PAGE = 0
.const : > RAMGS5, PAGE = 1
.data : > RAMGS5, PAGE = 1
.sysmem : > RAMGS5, PAGE = 1
#else
.pinit : > RAMM0, PAGE = 0
.ebss : > RAMLS5, PAGE = 1
.econst : > RAMLS5, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
#endif

.TI.ramfunc : {} > RAMM0, PAGE = 0
dclfuncs : {} > RAMM0, PAGE = 0

ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1

/* The following section definitions are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333

SFRA_F_Data : > RAMGS2, ALIGN = 64, PAGE = 1

SFRA_Data : > RAMGS2, ALIGN = 64, PAGE=1

FPUmathTables : >> RAMD0, PAGE = 0

.scratchpad : > RAMLS0LS1, PAGE = 1
.bss_cla : > RAMLS0LS1, PAGE = 1
controlVariables : > RAMLS0LS1, PAGE = 1

cntl_coeff_RAM : > RAMGS3, PAGE = 1
cntl_var_RAM : > RAMGS2, PAGE = 1

cntl_coeff_RAM2 : > RAMGS3, PAGE = 1
cntl_var_RAM2 : > RAMGS2, PAGE = 1

//.DataBufferFDL: >> RAMGS10 | RAMGS11, PAGE = 1, ALIGN(4)
.DataBufferFDL: > RAMGS10_GS11, PAGE = 1

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/