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TMS320F28386D: Asynchronism between PWM and timer

Clément Letonnelier
Expert 2686 points
Part Number: TMS320F28386D

Hello,

Some info about our design to understand the question:

  • CPU runs @ 200MHz
  • CPU timers 0 generates an interrupt at 10kHz so TBPRD was set at 20000
  • EPWM instance is configured to generate a 20kHz PWM with counter in up-down mode so TBPRD was set at 5000

To check the synchronicity between our real-time interrupt and the PWM, we toggle a GPIO every cycle.

We were expecting our PWM signal to be synchronous with the GPIO, i.e. fixed offset in between both with obviously a little jitter.

However, in that configuration we observe that both are shifting one from the other over time.

This shifting disappears if we set the CPU timer 0 TBPRD register to 19999 which does not fully make sense wrt. the TRM.

Are our assumptions from the design at the top of the post correct ? Or did we miss something in the TRM.

Thanks,

Clément

  • 0
    TI__Genius 9171 points

    Hello Clément,

    Do you have an image of the oscilloscope readings or similar displaying this behavior?

    Regards,

    Jason Osborn

  • 0 in reply to Jason Osborn
    Expert 2686 points

    Hello Jason,

    An image wouldn't be showing the issue, a video would but it's complicated for me to do one due to security restrictions.

    What wasn't clear in my explanations ?

    What we basically saw was that with the configuration specified at the top where we were expecting the PWM and generated signal to be synchronous due to the timer and PWM period being multiples but when triggering on one the other was moving. However, with the minus one on the timer period (not logical as per the TRM to obtain the desired frequencies) both are synchronous.

    So maybe it's a problem of configuration of TBPRD registers but we followed the TRM instructions and don't understand why we need to put minus one in the timer TBPRD to have the signals synchronous one with the other.

    Clément

  • 0 in reply to Clément Letonnelier
    TI__Genius 9171 points

    Hello,

    Can you tell me how the PWM interrupt is triggering? i.e. what the Event Trigger settings are, particularly the ETSEL[INTSEL] register.

    Ignore this post, see below.

    Regards,

    Jason Osborn

  • +1 in reply to Jason Osborn
    TI__Genius 9171 points

    Actually, apologies- I think I have a better way to explain what I believe to be the source of the confusion.

    Essentially, the CPU timers can be thought of as a simple up-count timer- they count up from 0 to a target value, then reset back to 0. Take a look at Figure 26-6 in section 26.4.3 Calculating PWM Period and Frequency of the device's TRM:

    If we imagine that the ePWM up-counter here is instead the CPU timer, let's compare that to the up-down-counter, and let's take a look at the TPWM calculations for each. Does this make it a little more clear what you're looking at?

    Regards,

    Jason Osborn

  • 0 in reply to Jason Osborn
    Expert 2686 points

    Hello Jason,

    Yes it does make it more clear, this is what we thought from our investigations but wanted to make sure.

    Anyways, the fact that for a timer Ttimer = (PRD + 1) x Tsysclk is stated nowhere (not in the TRM and not in the driverlib CPUTimer_setPeriod function documentation), so that could be something worth stating.

    Best regards,

    Clément