Part Number: TMS320F28388D
Hi
My customer is developing F28388D.
Now, Softwere operate this:
CPU2 watchdog generate global interrupt(NMI) to CPU1.
CPU1 interrput function generate softwere reset( SIMRESET Register) .
Question1: In this settiong, After CPU1 wake up, can CPU1 read CPU2's RESC Register?
Question2: In Q1 setting, After CPU1 wake up, How to CPU1 knows that reset was started by CPU2 watchdog?
(I think CPU2's RESC Register shows NOT watchdog. Because reset was generated by softwere.)
Question3: In Q1 setting, Is there any way to CPU1 knows CPU2 watchdog had overflowed before reset?
Question4: If CPU2 watchdog is seted to reset mode, and generat CPU2 reset, CPU1 does not reset?
Question5: In Q4 setting, Is there any way to reset CPU1 with CPU2's reset?
Thanks,
GR