TMS320F28388D: Simulation For SDRAM signal using TMS320F28388DZWT controller. able to Observe Non-Monotocity

There is another post on same topic from you. 

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1213437/tms320f28388d-non-monocity-in-address-signal-for-sdram-using-tms320f28388dzwt-controller

Vivek Singh

Have you looked at this appnote which has detail about EMIF hardware reference design ?

Regards,

Vivek Singh

Yes, referred appnote- Design and Usage Guidelines for the C2000 External Memory Interface (EMIF). But in this application note it consist of 2 or more SDRAM for which T-placement or Inline Placement is Suggested.

But in my design it is point to point topology, which consist of only one SDRAM.

 Design_Guidelines_EMIF.pdf

Kindly guide how to eliminate Non-monotocity in the Signa for point-to-point topology(which as only one SDRAM).

Thanks and regards,

Haripriya S M

Yes.

We as well as many other customers have used even single SDRAM (or ASRAM) device and have not experienced any such issue. I'll discuss this with our board design experts and get back to you in couple of days.

Regards,

Vivek Singh

It would be really helpful if the solution is provided as soon as possible.

Thanks and Regards,

Haripriya S M  

Which IO models you are using for the simulation ? 

Simulation is carried out for SDRAM CKE signal.

Device f771682axzwt pin W11, model selector: BCF3385D_Driver_Mode_3p3.

sprm746a.ibs

Please find attached ibis model and setting information.

Thanks and regards,

Haripriya S M

Hi,

SDRAM is standard interface and there is lot's of data online available for board design. We can not think of anything specific to our design. Here is another appnote from TI which you can refer and see if that helps. 

Regards,

Vivek Singh

Hello Vivek,

From the appnote, It is Observed that SDRAM Clock as the non-monotocity Above and below the V measure. It would be really helpfull to understand how this signals are impacting in Hardware design.

Non-monotocity is accused due to impedance mismatch in the trace, which mainly depends on topology, termination and drive strength.

In our particular design the trace impedance is 50 Ohms, driver is having 63 Ohms of Impedance.

How to Match the impedance in this case?

Kindly help me through this.

It would be helpful if the schematic as Controller and SDRAM in same board with series termination placement.

Thanks and regards,

Haripriya S M

Sorry, I am not sure what to suggest on this. All the information should be available in IBIS model and the reference design provided in appnotes. I will check with our board design expert and see if they have any additional input.

Regards,

Vivek Singh 

Hi Haripriya,

I hope you were able to resolve this issue. Let us know if you have any further queries related to EMIF on this device.

Vivek Singh

Hello Vivek,

 One more observation was made in controller IBIS model.

While verifying the IBIS model checking file parser is giving 12 errors.

BCF3335D_WK_PU_ON_3P3': Ramp Not Defined

4401.sprm746a.ibs

Kindly help in resolving the issue.

Thanks and regards,

Haripriya SM 

Hi,

May I know which tool you are using ?

Vivek Singh

hello,

using HyperLynx tool

Haripriya S M

Ok, thank you. I have requested the info from our design team. Please expect an update in next couple of days.

Regards,

Vivek Singh

Sorry, our design team could not look into this due to some other priorities. I have requested them again to look into this issue. I hope to hear from them early next week.