Part Number: TMS320F28069
The attached code uses PWM2 to generate some test pulses of fixed frequency,10kHz and fixed duty cycle (40%).
The pulses are read in on GPIO13. XINT1 is enabled on GPIO13 with rising edge detection ON. So whenever the PWM2 pulse go high, XINT1 interrupt should trigger.
I also have PWM1 module enabled with a fixed freq of 500Hz. The PWM pin is driven high when CNT=COMPA and driven low when CNT=COMPB.
Also have a test GPIO21 toggle in XINT1 interrupt.
Whenever XINT1 interrupt is triggered, it resets the PWM1CNT to 0. So basically PWM1 should never see CNT=PRD as long as PMW2 is generating pulses.
Now all the above works great if I have to no other interrupts enabled. I see a fixed latency in XINT1 interrupt ISR call, which reflects on PWM1 pulse, and in test GPIO21.
Things starts to go bad as soon as I introduce one more interrupt, in the attached code its TIMER1 interrupt. Pretty low in CPU priority (17) compared to XINT1 interrupt priority (5), PIE Group 1.
I see jitter in XINT1 interrupt latency with a spread of about 300ns. The jitter seen in the attached PWM1 is the jitter that get propagated from XINT1. PMW1CNT resetting to 0 in XINT, so any jitter in XINT1 ISR will show up in PWM1 pulse.
I see same jitter in the test GPIO output pin 21 that is made to toggle in XINT1 ISR.
My question is why is the low priority interrupt causing jitter in the high priority interrupt latency? Attached are few video of my readings on oscilloscope.
Source Code:
/cfs-file/__key/communityserver-discussions-components-files/171/Example_5F00_2806xEPwmUpAQ.c
Oscilloscope videos:
PMW1 on D12, PWM2 on D9, GPIO21 on D8
/cfs-file/__key/communityserver-discussions-components-files/171/JitterInPWM.MOV
/cfs-file/__key/communityserver-discussions-components-files/171/JitterInGpio21.MOV
