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Original question:

TMS320F28377D: EMIF request arbitration details

TMS320F28377D: EMIF

Yale Li 李耀先
Expert 4660 points

Part Number: TMS320F28377D

Hi Team,

I ask this question for our customer:

If CPU1 wants to read and write two asynchronous devices, and CPU2 wants to read and write one asynchronous device. Are EMIF1 and EMIF2 unable to meet this requirement?

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Thanks & Regards

Yale

  • +1
    TI__Guru* 95315 points

    Only CPU1 has access to EMIF2. One Asynch device can be accessed through EMIF2 by CPU1.

    CPU1 and CPU2 both have access to EMIF1. Either CPU can claim the master ownership for EMIF1 by configuring the EMIF1MSEL register.

    EMIF1 supports 32-bit data bus where as EMIF2 has only 16-bit data bus.

    EMIF1 support up to 3 chip-select (CSx) signals and EMIF2 supports 1 CSx for ASRAM. Since there are 3 CSx signals for EMIF1, accessing two asynch memories is possible.