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Original question:

TMS320F2808: tms320f2808

TMS320F2808: Different methodes can cause anomalies in the data sent by SPI.

Gabriel Wang1
Genius 4555 points
Part Number: TMS320F2808
Other Parts Discussed in Thread: C2000WARE

Dear Expert

Problem description:
TMS320F2808 DSP SPI communication performs SPI transmission during interrupts with a cycle of 18KHz. The following two different methods can cause anomalies in the data sent by SPI.
The first method is to divide 18KHz into two 9KHz, and send the first 9KHz. The data to be transmitted is stored in SpiaRegs.SPITXBUF; Receive at the second 9KHz and read out the SpiaRegs. SPIRXBUF register data. The operation of SpiaRegs. SPITXBUF and SpiaRegs. SPIRXBUF will have a time interval of 55.56us. No abnormalities were found in the data sent by SPI under this working condition.
The second method is to perform operations on the SpiaRegs. SPITXBUF and SpiaRegs. SPIRXBUF registers every 18K. First, read the SpiaRegs. SPIRXBUF, perform data processing, and then store the data to be transmitted into SpiaRegs. SPITXBUF. The time interval between reading the SpiaRegs. SPIRXBUF and storing the data into SpiaRegs. SPITXBUF is approximately a few us. In this working situation, the data sent by SPI is abnormal.
Note: The state of SPI was not evaluated before reading SpiaRegs. SPIRXBUF and storing data in SpiaRegs. SPITXBUF.

  • 0
    TI__Mastermind 28111 points

    I don't fully understand your code flow. A few questions.

    1. What is your SPI data size and clock? You would to make sure that the SPI is running fast enough to complete transfers within the 18kHz time frame.

    2. Are you checking the SPI TXFFST bits, if using FIFO mode, before writing new values to SPITXBUF? If not using FIFO, are you checking the SPI INT FIFO flag before writing a new value to SPITXBUF?

  • 0 in reply to Gus Martinez
    Genius 4555 points

    Dear Gus 

    1. What is your SPI data size and clock? You would to make sure that the SPI is running fast enough to complete transfers within the 18kHz time frame.

    ->  SPI data size is 32bit, and SPI clock is 3.125MHz.

     

     

    1. Are you checking the SPI TXFFST bits, if using FIFO mode, before writing new values to SPITXBUF? If not using FIFO, are you checking the SPI INT FIFO flag before writing a new value to SPITXBUF?

    ->  We are not use the FIFO mode, and we are not check any spi flag befor writing a new value to SPITXBUF.

  • 0 in reply to Gabriel Wang1
    TI__Mastermind 28111 points

    You should use the SPI flags before writing new values to the SPITXBUF. Please reference the code examples provided with C2000ware.

    C:\ti\c2000\C2000Ware_4_03_00_00\device_support\f2802x\examples\structs\spi_loopback

    C:\ti\c2000\C2000Ware_4_03_00_00\device_support\f2802x\examples\drivers\spi_loopback

  • 0 in reply to Gus Martinez
    Genius 4555 points

    Dear Gus

     

    Thanks for your information. I still have some questions: 

    1. I have to prioritize SPITXBUF, the SPIRXBUF is not that strict, the SPI write SPITXBUF and read SPIRXBUF in interrupt. So I can't get the SPI flags befor writing new value to the SPITXBUF. Do you have some good idea?
    2. If SPI receive many buffer but I can't read the SPIRXBUF in time, It will not cause the wrong overflow error or other error?
  • 0 in reply to Gabriel Wang1
    TI__Mastermind 28111 points
    Gabriel Wang1 said:
    I have to prioritize SPITXBUF, the SPIRXBUF is not that strict, the SPI write SPITXBUF and read SPIRXBUF in interrupt. So I can't get the SPI flags befor writing new value to the SPITXBUF. Do you have some good idea?

    You cannot write new data to SPITXBUF is the TX_BUF_FULL_FLAG is set. If you do, you will overwrite the previous data. You have to check this flag before writing data to SPITXBUF.

    Gabriel Wang1 said:
    If SPI receive many buffer but I can't read the SPIRXBUF in time, It will not cause the wrong overflow error or other error?

    Yes.

    Are you using the SPI in slave mode? If so, how does the 18kHz ISR you mention relate to the speed at which the SPI master is requesting data? In other words, how do you ensure the SPITXBUF always has data ready before the SPI master starts a new transaction? 

  • 0 in reply to Gus Martinez
    Genius 4555 points

    Dear Gus

    Are you using the SPI in slave mode? If so, how does the 18kHz ISR you mention relate to the speed at which the SPI master is requesting data? In other words, how do you ensure the SPITXBUF always has data ready before the SPI master starts a new transaction? 

     

    -> No, We use master mode in DSP2808. The SPI slave object is FPGA, FPGA answer data when master transmit every times.

  • 0 in reply to Gabriel Wang1
    TI__Mastermind 28111 points

    Thanks for clarification. In this case, the following sequence can be followed to send 32 bits to the SPI slave.

    • CPU waits SPI TX BUFF FULL == 0  // ensure SPITXBUF is not full
    • CPU writes 16 bits SPITXBUF
    • CPU waits SPI INT FLAG == 1  // wait for SPI to receive 16 bits from slave
    • CPU reads 16 bits SPIRXBUF
    • CPU waits SPI TX BUFF FULL == 0 // ensure SPITXBUF is not full
    • CPU writes 16 bits SPITXBUF
    • CPU reads 16 bits SPIRXBUF // wait for SPI to receive 16 bits from slave