This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
In the ERAD example for profiling, the ERAD_getMaxCount is used for getting the cycle count. The following comment can be seen:
// Note that calling the function ERAD_getCurrentValue here will
// return 0 since the stop events have already been occurred.
What would be the procedure to find out the average and minimum count?
Hello Ganesh,
There is no average or minimum count function in the ERAD hardware. You would need to compute these in software if you needed to.
Also, please note that the MAX_COUNT register only works in start-stop mode with the cumulative count setting disabled.
Thanks,
Ibukun
Could you please elaborate on computing using software? It would be good if you provide an example.
Also, in the case of start-stop mode, the TRM doesn't mention what happens in the event of reaching maximum count:
What if the stop event occurs after reaching the maximum value of the counter? Does it reset to zero and count up and does this have a flag?
Hello Ganesh,
First to be clear - MAX_COUNT is different from "maximum value" as referenced in the TRM section above. MAX_COUNT reports the highest counter value that has been recorded across multiple start-stop SEC executions. For example, if you had the SEC configured in start-stop mode and had four events triggering the counter that resulted in counts of 300, 350, 370 and 330 cycles respectively, then MAX_COUNT would have a value of 370. MAX_COUNT is automatically updated by hardware whenever a new higher cycle count has been recorded. My point earlier was that hardware does not similarly track the "MIN_COUNT" or average. To get these, you would have to record the individual counter values in software (e.g., using an interrupt triggered by the counter stop event), and then find the minimum or average.
Regarding the TRM section above: this text describes what happens when the CTM_COUNT register overflows (reaches 0xFFFFFFFF). In this case it resets to 0, the CTM_STATUS.OVERFLOW bit is set high, and it continues counting. This overflow behavior is not dependent on the counter mode. We will update the documentation to make this clearer.