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Hi all,
I'm trying to optimize some assembly routines and wondering how the pipeline would look like using RPT instructions.
To be more precise, here is a part of an assembly routine with a pipeline diagram (which should be right in my understanding):
Instr. | Ops. | Address | Opcode | Instruction # |
MOVL | XAR7, ACC | 0x008DAB | 1EA7 | I1 |
MOVL | XAR6, XAR4 | 0x008DAC | C4A4 | I2 |
DEC | AR5 | 0x008DAD | 0BA5 | I3 |
ZAPA | 0x008DAE | 5633 | I4 | |
RPT | AR5 | 0x008DAF | F7A5 | I5 |
||MINL | ACC, *XAR4++ | 0x008DB0 | 56500084 | I6 |
PIPELINE | ||||||||
F1 | F2 | D1 | D2 | R1 | R2 | E | W | CPU Cycles |
0x008DAB | 1 | |||||||
0x008DAC | 1EA7 | 1EA7 | 2 | |||||
0BA5:C4A4 | C4A4 | XAR7 = ACC | 3 | |||||
0x008DAE | 0BA5 | XAR6 = XAR4 | - | 4 | ||||
F7A5:5633 | 5633 | AR5 = AR5 - 1 | - | - | 5 | |||
0x008DB0 | F7A5 | ACC = 0, P = 0, OVC = 0 | - | - | - | 6 | ||
56500084 | 56500084 | RPTC = AR5 | - | - | - | - | 7 | |
Generate source address | - | - | - | - | 8 | |||
Drive address | - | - | - | 9 | ||||
Read data pointed to by XAR4 | - | - | 10 | |||||
ACC = MIN(ACC, [XAR4]) | - | 11 |
What happens at the next execution of MINL instruction?
Many thanks.
Paolo
Paolo Benini said:What happens at the next execution of MINL instruction?
Many thanks.
MINL will be pushed back through the pipeline at D2 immediately behind the previous MINL. There is no re-fetch associated with RPT.
Regards,
Lori