• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 323 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: How is the ADC sampling rate of this model calculated at a maximum of 3.5Msps?

Ben Qin
Intellectual 2690 points
Part Number: TMS320F28379D

Hi Team,

As in the title, how to calculate in single-ended mode, the maximum sampling rate of a single ADC is 3.5Msps, which is not mentioned in the manual.

Thanks & Regards,

Ben

  • 0
    TI__Mastermind 30185 points

    Hello Ben,

    To calculate the ADC sample rate, add the chosen ACQPS value in seconds with the tEOC (also in seconds) and then take the inverse of this number:

    Sample rate = 1 / (ACQPS + tEOC)

    ACQPS: Sample-and-hold time; minimum of 75 ns based on hardware, provided by the datasheet (8.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode))

    tEOC: Time from the end of the sample-and-hold window until the nextADC conversion can begin; provided in SYSCLKs, with a minimum of 44 based on the device frequency and maximum ADC clock frequency (provided by the datasheet in section 8.10.1.2.3 ADC Operating Conditions (12-Bit Single-Ended Mode))

    Make sure the ACQPS and tEOC are in the same units before using them in the above equation (here I've assumed you were talking about 12-bit single-ended mode). Let me know if you have any questions about this.

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    TI__Intellectual 2690 points

    Hi Omer,

     I agree that the maximum sampling rate is calculated in this way, but in the routine of C200wave, adc_ex2_soc_epwm.c, the sampling window (ACQPS) of this routine is 15 clock cycles, which is 75ns. I change the frequency of epwm to control the sampling rate of the ADC, but the maximum speed can only reach about 500Ksps~600Ksps. How can I achieve a controllable sampling rate of about 3M?

    The figure below is the sampling rate I configured according to the routine adc_ex2_soc_epwm.c, and the waveform read will be incorrect no matter how high it is.

    Best Regards,

    Ben

  • 0 in reply to Ben Qin
    TI__Mastermind 30185 points

    Hello Ben,

    This example only uses 1 ADC, which will have some delay because it's doing 1 conversion and then reading that result. The best way to try and achieve a higher sampling rate is using many SOCs (all if possible). You can trigger the first SOC however you want and then have each EOC trigger the next SOC so that you are getting continuous conversions. If you are having the ePWM trigger each conversion on 1 SOC, the throughput of the ADC will most likely be lower than the maximum possible.

    Also, keep in mind that depending on how long the ISR is (this example seems okay, but a customer use-case may vary), the sampling rate may be affected as well as the accuracy of the result.

    Best regards,

    Omer Amir

  • 0 in reply to Omer Amir
    TI__Intellectual 2690 points

    Hi Omer,

    Well, when I tried routine adc_ex6_soc_continuous_dma, I also found that the sampling rate can reach 2Msps, but if I need to design the ADC to have a high and controllable sampling rate, the sampling rate during continuous sampling seems uncontrollable. Is there any way to solve this problem?

    Best Regards,

    Ben

  • 0 in reply to Ben Qin
    TI__Mastermind 30185 points

    Hello Ben,

    How are you measuring the sampling rate as an observable value? Are you reading an input and then determining the sample rate from that, are you using the graph tool in the CCS debug session, or is there some other method you're using?

    Best regards,

    Omer Amir