TMS320F280049: abnormal pwm pulse

Hello,

What count mode are you using? What are your action qualifier settings? Are you updating settings each period? Do these values ever change?

Thank you,

Luke

Hi Luke,

Thanks for you  focus on my issue.

The count mode is up and down,  my action qualifier setting is: CTR = CMPA@UP , xA set to 1， CTR = CMPA@Down , xA set to 0,  

Yes, I updating setting each period, only phase shift value change other's value not change(such as period，duty，deadtime)

best&regards

lucas

Hi Luke,

I'm not very undestand your solution, I list as below:

(1)How to set the sync input signal as the T1 trigger source? and what's the T1 ?

(2)How to set an action qualifier event on T1?

(3) you mean when TBPHS is greater than CMPA then use ction qualifier force pwm keep low? but I think it will affect the controller performance, , my phase shift algorithom will run during 0 - 180degree， and the CMPA is 50% equal to 90degree，that means it only run arange 0-

90degree? if so , the algorithom will not run correctly.

best&regards

lucas

Hi Lucas,

1) This is selected via the AQTSRCSEL[T1SEL] bitfield. T1 is an event that can come from the comparator module, trip-zone submodule, or EPWM sync signals as an input to the action qualifier module.

2) AQCTLA2 and AQCTLB2 control the behavior of outputs A and B on a T1 event

3) I am suggesting using the T1 event as an action qualifier event in this case. How would this workaround affect controller performance? The action qualifier event induced by the sync event should be identical to the CMPA event, it should not affect your output except for when the CMPA action qualifier event is skipped due to a large jump in TBCTR caused by the sync event.

Could you elaborate on how this workaround would affect controller performance?

Thank you,

Luke

Hi Luke,

I have a try about your soloution, the code as below:  this part code runs each period.

"dutyASec_ticks"  is the CMPA value ,and the"phaseShiftPrimSec_ticks_d2"  is the phase shift value, as your suggestion, when dutyASec_ticks < phaseShiftPrimSec_ticks_d2 , I set the pwm syncin as the T1 source,and set the AQ force A and B keep low when EPWM_AQ_OUTPUT_ON_T1_COUNT_UP , am I do right? But I found the result still will lost PWM somtimes.

if(dutyASec_ticks < phaseShiftPrimSec_ticks_d2)
{
        EPWM_setActionQualifierAction(SEC_LEG1_PWM_BASE,EPWM_AQ_OUTPUT_A,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(SEC_LEG1_PWM_BASE,EPWM_AQ_OUTPUT_B,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierT1TriggerSource(SEC_LEG1_PWM_BASE,EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN);
}
else
{
HWREG(SEC_LEG1_PWM_BASE + HRPWM_O_TBPHS) = phaseShiftPrimSec_ticks_d2;
}

best &regards

lucas

Hi Lucas,

Your code to modify the action qualifier settings looks correct.

I have another suggestion. If my theory about the sync pulse skipping over the CMPA event is correct, the 100 percent duty cycle should only occur the first time that TBPHS exceeds CMPA, and not again until after TBPHS is configured to be less than CMPA again. I suggest that you create another variable containing a boolean value, so that the code you've included above only occurs when there is a change in the truth value of (dutyASec_ticks < phaseShiftPrimSec_ticks_d2). In addition to this, I would set a breakpoint after the action qualifier settings have been changed and check if this occurs at the same time your scope is triggered by the longer duration of a high EPWM output as shown in your original screenshot.

If this issue is not caused by synchronization, my only other suspicion is that you have a CBC trip event that is forcing the EPWM output to a high state for an extra cycle. Do you have any trip-zone configuration in your system that would make this possible?

Hi luke,

I check the code ,I didn't use CBC trip event.

I have a founding: when I change above code "EPWM_setActionQualifierAction(SEC_LEG1_PWM_BASE,EPWM_AQ_OUTPUT_A,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_T1_COUNT_UP) and EPWM_setActionQualifierAction(SEC_LEG1_PWM_BASE,EPWM_AQ_OUTPUT_B,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_T1_COUNT_UP)"  to (SEC_LEG1_PWM_BASE,EPWM_AQ_OUTPUT_A,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN) and EPWM_setActionQualifierAction(SEC_LEG1_PWM_BASE,EPWM_AQ_OUTPUT_B,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN),the PWM seem normal. 

So my question is why change EPWM_AQ_OUTPUT_ON_T1_COUNT_UP to  EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN the PWM become normal?

Another founding is:  even though the pwm not missing again,but when TBPHS > CMPA  with above solution,the  slave PWM always keep the same phase with master PWM, so why this performance? I thought it shouldn't affect the phase shift behavior.

best & regards

lucas