TMS320F28388D: EtherCAT Can`t Sacn

Hi,

wangbengang said:

As I continue to test, I have found the following pattern:

1. I used the SYSPLL clock for EtherCAT configuration and turned off the AUXPLL clock, which worked fine.
2. I configured EtherCAT to use a SYSPLL clock and configured the AUXPLL clock to run at 125MHz and it didn't work properly
3. I configured EtherCAT to use SYSPLL clocks and configured AUXPLL clocks at 400MHz or 500MHz, which worked fine

Are you using AUXPLL to clock any device peripherals and/or CM core in these tests? By AUXPLL you are meaning AUXPLLRAWCLK in the clock diagram of the TRM, correct?

wangbengang said:

• 1. I used a SYSPLL clock for EtherCAT, and the AUXPLL clock was configured at 125MHz, which was not working properly, and TwinCAT often failed to scan the slave station
  2. I used a SYSPLL clock for EtherCAT, and the AUXPLL clock was configured to 500MHz, which worked fine.
• I found that if you configure AUXPLL at slower frequencies, such as 100MHz, 125MHz. And running it alone in Flash makes EtherCAT unstable.
• I want to know why this is a problem?

Our ECAT module requires 100MHz clock input at the point below, keep in mind. Is this being met in your tests?

Best,

Kevin

1. When I ran my tests on CPU1, AUXPLLRAWCLK had no drive peripherals or CM cores. When I run on the CM side, AUXPLLRAWCLK drives the CM core. Similar problems occur in both cases.
2. I configured SYSPLL to 200MHz, EtherCAT module to use SYSPLL, and ECATDIV to 2. And once scanned, everything works fine.   
3. SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_2, SYSCTL_SOURCE_SYSPLL, ESC_USE_INT_PHY_CLK);

Hi,

wangbengang said:

• I found that if you configure AUXPLL at slower frequencies, such as 100MHz, 125MHz. And running it alone in Flash makes EtherCAT unstable.
• I want to know why this is a problem?

You mention this issue only occurs when running standalone from flash and with lower AUXPLL frequencies. Did you try with 250MHz AUXPLLRAWCLK?

Are you using the ControlCard Evaluation Board or a custom board? What is your external clock source to the F2838x device? i.e. crystal or single-ended oscillator, frequency of the device, etc.

Best,

Kevin

I tried the AUXPLLRAWCLK 250MHz frequency and it worked fine.

I currently have two versions of the board and the problem is the same. One board uses 20MHz crystal for the TMS320F28388, and two 25MHz crystal for the PHY chip. The other board uses a 25MHz crystal to feed the TMS320F28388 and PHY chip.

Hi,

wangbengang said:

I tried the AUXPLLRAWCLK 250MHz frequency and it worked fine.

OK, thanks for checking.

wangbengang said:

I currently have two versions of the board and the problem is the same. One board uses 20MHz crystal for the TMS320F28388, and two 25MHz crystal for the PHY chip. The other board uses a 25MHz crystal to feed the TMS320F28388 and PHY chip.

The first board is not a recommended clocking method, see below from Beckhoff Application Note – PHY Selection Guide. The ESC and two PHYs should share a common clock source.

For the 2nd board, are you using a passive crystal component (i.e. does not require power)? If so, this wouldn't be recommended either as the clock integrity cannot be maintained for all connected devices. You should use an active / powered 25MHz single-ended oscillator instead (+/- 25ppm requirement per Beckhoff), ideally with an additional clock buffer.

You can review our F2838x or F28P65x ControlCard board designs for reference.

Best,

Kevin

Hi,

Can you check what you're locking the PLL VCO at? It's minimum is 220MHz.

Best,

Kevin

Hi，

• This is a schematic of my second version of the board,

• My clock configuration is as follows, I used the clock macro definition in device.h so that the PLL VCO should be configured at 500MHZ

Best

Hi,

wangbengang said:

This is a schematic of my second version of the board,

This looks good to me.

wangbengang said:

My clock configuration is as follows, I used the clock macro definition in device.h so that the PLL VCO should be configured at 500MHZ

Yes, this looks OK as well.

Best,

Kevin

Hi,

So I don't know why there is this problem, and it won't happen if you only modify AUXPLLCLK.

I was wondering if there would be any problem with using the official development board and changing the clock to look like mine.

Best

Hi,

wangbengang said:

I was wondering if there would be any problem with using the official development board and changing the clock to look like mine.

The ControlCard Eval board can be used to check this. Do you have one to test with yourself?

If not, I can try it and get back to you.

Best,

Kevin

Hi,

I don't have a ControlCard Eval board now.Would you mind testing it?

Using the EtherCAT master routine, AUXPLL is set to 125MHz and burned into Flash to boot.

Best,

Hi,

I tested the following conditions with TMDSCNCD28388D. Both worked fine and I was able to scan and put in OP mode using TwinCAT.

Software: 'f2838x_cpu1_allocate_ecat_to_cm' and 'f2838x_cm_echoback_solution' (Only tried CM ECAT)

1. 500 MHz AUXCLK:

   1. // 500MHz
      SysCtl_setAuxClock(SYSCTL_AUXPLL_ENABLE | SYSCTL_AUXPLL_OSCSRC_XTAL_SE |
                         SYSCTL_AUXPLL_IMULT(20) | SYSCTL_AUXPLL_FMULT_0 |
                         SYSCTL_AUXPLL_DIV_1);
                         
      // 200MHz / 2 = 100MHz
      SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_2, SYSCTL_SOURCE_SYSPLL,
                        ESC_DISABLE_INT_PHY_CLK);

2. 125 MHz AUXCLK:

   1. // 125MHz
      SysCtl_setAuxClock(SYSCTL_AUXPLL_ENABLE | SYSCTL_AUXPLL_OSCSRC_XTAL_SE |
                         SYSCTL_AUXPLL_IMULT(40) | SYSCTL_AUXPLL_FMULT_0 |
                         SYSCTL_AUXPLL_REFDIV(2U) | SYSCTL_AUXPLL_ODIV(4U) |
                         SYSCTL_DCC_BASE_0 | SYSCTL_AUXPLL_DIV_1);
                         
      // 200MHz / 2 = 100MHz
      SysCtl_setECatClk(SYSCTL_ECATCLKOUT_DIV_2, SYSCTL_SOURCE_SYSPLL,
                        ESC_DISABLE_INT_PHY_CLK);

Best,

Kevin

Hi,

Is it running in Flash and not connected to an emulator?

Best,

Yes. I had both 'f2838x_cpu1_allocate_ecat_to_cm' and 'f2838x_cm_echoback_solution' running from flash.  First I tried with emulator connected and then I power cycled the board to test standalone flash operation. Both worked OK, being able to scan the device in TwinCAT and put into OP mode when using free-run mode (I did not try with real-time mode / Distributed Clocks).

Best,

Kevin

Hi,

Thank you very much, but we have different phenomena, I will wait for our next version of the board to test again.

Best

Hi,

Maybe it is the clock source design. Your new board design more closely matches what we do in our evaluation boards, with the 25MHz oscillator + clock buffer device. Please plan to try with a +/- 25PPM spec'd oscillator, Beckhoff states this is required for certain EtherCAT features / functions.

Best,

Kevin