Hi,
I am using TMS320F2812 with external 128kB RAM and CCSV5.0 (I have migrated the code from CCSV3 to CCS V5.0). If I use default linker file(F2812 Flash.cmd) file from repository then there is no error in compiling, but micro is getting reset during debugging.
If I am using below code in F2812 Flash.cmd as specified in one of document which I received from KT
MEMORY
{
PAGE 0: /* Program Memory */
RAML0 : origin = 0x008000, length = 0x000A00 /* on-chip RAM block L0 */
ZONE2 : origin = 0x080000, length = 0x010000 /* XINTF zone 2 */
FLASHALL : origin = 0x3D8000, length = 0x01E000
ENDFLASH : origin = 0x3F6000, length = 0x000004
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /*Program with all 0x0000 when CSM is in
use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Used for "boot to Flash" bootloader
mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* CSM password locations in FLASHA */
ROM : origin = 0x3FF000, length = 0x000FC0 /* Boot ROM available if MP/MCn=0 */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM (MP/MCn=0) or
XINTF zone 7 (MP/MCn=1) */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM (MP/MCn=0) or
XINTF zone 7 (MP/MCn=1) */
PAGE 1 : /* Data Memory */
ZONE2DAT : origin = 0x090000, length = 0x010000 /* XINTF zone 2 data */
RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML1 : origin = 0x008A00, length = 0x0015F7 /* on-chip RAM block L1 */
TST_LOC : origin = 0x009FF8, length = 9 /* used for ram health test */
RAMH0 : origin = 0x3F8000, length = 0x002000 /* on-chip RAM block H0 */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHALL PAGE = 0
.pinit : > FLASHALL PAGE = 0
.text : > FLASHALL PAGE = 0
config : > FLASHALL PAGE = 0
initXintf : > FLASHALL PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : { Filter.lib < iir32.obj> (.text), fft.lib < cfft32i.obj, cfft32c.obj, rfft32aq.obj, rfft32w.obj,
rfft32s.obj, rfft32m.obj >(.text)}
LOAD = FLASHALL,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_END(_RamfuncsRunEnd),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
iirfilt : > RAMM1 PAGE = 1
FFTipcb1A ALIGN(1024):{} >RAMH0 PAGE = 1
FFTipcb1B ALIGN(1024):{} >RAMH0 PAGE = 1
FFTipcb2A ALIGN(1024):{} >RAMH0 PAGE = 1
FFTipcb2B ALIGN(1024):{} >RAMH0 PAGE = 1
FFTtf > FLASHALL PAGE = 0
flash_sum : > ENDFLASH PAGE = 0
/* Allocate uninitalized data sections: */
.stack
.ebss
: > RAMM0 PAGE = 1, END( _TopOfStack )
: > RAML1 PAGE = 1
.esysmem : > RAMH0 PAGE = 1
TstLoc : > TST_LOC PAGE = 1
FSData : > RAML1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHALL PAGE = 0
.switch : > FLASHALL PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHALL PAGE = 0 /* Math Code */
IQmathTables : > ROM PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
I am facing below error code while compiling -
Description Resource Path Location Type
<a href="file:/C:/ti/ccs1240/ccs/tools/compiler/dmed/HTML/10099.html">#10099-D</a> program will not fit into available memory. run placement with alignment/blocking fails for section ".stack" size 0x4b0 page 1. Available memory ranges: F2812 FLASH.cmd /Exacta line 149 C/C++ Problem
Requested to help me to resolve the same. Please let me know if any other information required and thanks in advance
Regards,
Sudhir Jangra
