Part Number: TMS320F28335
Dear Expert,
I am attempting to send a sequence of characters consecutively using FIFO and Interrupts in SCI-A and SCI-B. The problem is that the SCI-A is the only interrupt working, while the SCI-B interrupt, being at a lower level, does not seem to get called/triggered at all. (the value of count_b_S to count_b_D is just 0, and so does the receive_b_count)
I have based my code on the modified version of the example program "Example_2833xSci_FFDLB_int." The configuration includes a baud rate of 9600 (LSPCLK = 75 MHz), and the code is operating in loopback mode.
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
// Prototype statements for functions found within this file.
interrupt void sciaTxFifoIsr(void);
interrupt void sciaRxFifoIsr(void);
interrupt void scibTxFifoIsr(void);
interrupt void scibRxFifoIsr(void);
void scia_fifo_init_user();
void scib_fifo_init_user();
// Global variables
Uint16 sdataA[16]; // Send data for SCI-A
Uint16 sdataB[16]; // Send data for SCI-B
Uint16 rdataA[16]; // Received data for SCI-A
Uint16 rdataB[16]; // Received data for SCI-B
int send_a_count = 0;
int send_b_count = 0;
int receive_a_count = 0;
int receive_b_count = 0;
char receive_a_char[17];
char receive_b_char[17];
Uint16 count_a_S = 0;
Uint16 count_a_plus = 0;
Uint16 count_a_0 = 0;
Uint16 count_a_1 = 0;
Uint16 count_a_2 = 0;
Uint16 count_a_3 = 0;
Uint16 count_a_4 = 0;
Uint16 count_a_5 = 0;
Uint16 count_a_6 = 0;
Uint16 count_a_7 = 0;
Uint16 count_a_8 = 0;
Uint16 count_a_9 = 0;
Uint16 count_a_A = 0;
Uint16 count_a_B = 0;
Uint16 count_a_C = 0;
Uint16 count_a_D = 0;
Uint16 count_b_S = 0;
Uint16 count_b_plus = 0;
Uint16 count_b_0 = 0;
Uint16 count_b_1 = 0;
Uint16 count_b_2 = 0;
Uint16 count_b_3 = 0;
Uint16 count_b_4 = 0;
Uint16 count_b_5 = 0;
Uint16 count_b_6 = 0;
Uint16 count_b_7 = 0;
Uint16 count_b_8 = 0;
Uint16 count_b_9 = 0;
Uint16 count_b_A = 0;
Uint16 count_b_B = 0;
Uint16 count_b_C = 0;
Uint16 count_b_D = 0;
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
EALLOW;
SysCtrlRegs.LOSPCP.bit.LSPCLK = 1;
EDIS;
// HISPCP prescale register settings, normally it will be set to default values
EALLOW; // This is needed to write to EALLOW protected registers
SysCtrlRegs.HISPCP.all = 0x0000;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//InitGpio();
// Setup only the GP I/O only for SCI-A and SCI-B functionality
// This function is found in DSP2833x_Sci.c
InitSciaGpio();
InitScibGpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
PieVectTable.SCITXINTA = &sciaTxFifoIsr;
PieVectTable.SCIRXINTB = &scibRxFifoIsr;
PieVectTable.SCITXINTB = &scibTxFifoIsr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
scia_fifo_init_user(); // Init SCI-A
scib_fifo_init_user(); // Init SCI-B
// Step 5. User specific code:
// Enable EPWM1_INT in the PIE: Group 3 interrupt 1
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // PIE Group 9, INT1, SCIRXINTA
PieCtrlRegs.PIEIER9.bit.INTx2 = 1; // PIE Group 9, INT2, SCITXINTA
PieCtrlRegs.PIEIER9.bit.INTx3 = 1; // PIE Group 9, INT3, SCIRXINTB
PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // PIE Group 9, INT4, SCITXINTB
IER |= M_INT9; // Enable INT9 of CPU
EINT; // Enable Global interrupt INTM
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;);
}
void scia_fifo_init_user()
{
SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity, 8 char bits,
// async mode, idle-line protocol
SciaRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
SciaRegs.SCICTL2.bit.TXINTENA = 1;
SciaRegs.SCICTL2.bit.RXBKINTENA = 1;
SciaRegs.SCIHBAUD = 0x0003; // 9600 baud @LSPCLK = 75MHz.
SciaRegs.SCILBAUD = 0x00CF;
SciaRegs.SCICCR.bit.LOOPBKENA = 1; // Enable loop back
//SciaRegs.SCIFFTX.all = 0xC028;
//SciaRegs.SCIFFTX.all = 0xC029;
//SciaRegs.SCIFFTX.all = 0xC02F;
SciaRegs.SCIFFTX.all = 0xC030;
//SciaRegs.SCIFFRX.all = 0x0028;
//SciaRegs.SCIFFRX.all = 0x0029;
SciaRegs.SCIFFRX.all = 0x0030;
SciaRegs.SCIFFCT.all = 0x00;
SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
}
void scib_fifo_init_user()
{
ScibRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity, 8 char bits,
// async mode, idle-line protocol
ScibRegs.SCICTL1.all = 0x0003; // enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScibRegs.SCICTL2.bit.TXINTENA = 1;
ScibRegs.SCICTL2.bit.RXBKINTENA = 1;
ScibRegs.SCIHBAUD = 0x0003; // 9600 baud @LSPCLK = 75MHz.
ScibRegs.SCILBAUD = 0x00CF;
ScibRegs.SCICCR.bit.LOOPBKENA = 1; // Enable loop back
//ScibRegs.SCIFFTX.all = 0xC028;
//ScibRegs.SCIFFTX.all = 0xC029;
//ScibRegs.SCIFFTX.all = 0xC02F;
ScibRegs.SCIFFTX.all = 0xC030;
//ScibRegs.SCIFFRX.all = 0x0028;
//ScibRegs.SCIFFRX.all = 0x0029;
ScibRegs.SCIFFRX.all = 0x0030;
ScibRegs.SCIFFCT.all = 0x00;
ScibRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
ScibRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
ScibRegs.SCIFFRX.bit.RXFIFORESET = 1;
}
interrupt void sciaTxFifoIsr(void)
{
sdataA[0] = (int)'S';
sdataA[1] = (int)'+';
sdataA[2] = (int)'0';
sdataA[3] = (int)'1';
sdataA[4] = (int)'2';
sdataA[5] = (int)'3';
sdataA[6] = (int)'4';
sdataA[7] = (int)'5';
sdataA[8] = (int)'6';
sdataA[9] = (int)'7';
sdataA[10] = (int)'8';
sdataA[11] = (int)'9';
sdataA[12] = (int)'A';
sdataA[13] = (int)'B';
sdataA[14] = (int)'C';
sdataA[15] = (int)'D';
if (SciaRegs.SCIFFTX.bit.TXFFST == 0) {
Uint16 ka;
for(ka = 0; ka < 16; ka++) {
SciaRegs.SCITXBUF = sdataA[ka]; // Send data
}
}
send_a_count++;
SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1; // Clear SCI Interrupt flag
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ACK
}
interrupt void sciaRxFifoIsr(void)
{
Uint16 karx;
for (karx = 0; karx < 16 ; karx++) {
rdataA[karx] = SciaRegs.SCIRXBUF.bit.RXDT; // Read data
if (rdataA[karx] == (int)'S') {
++count_a_S;
}
if (rdataA[karx] == (int)'+') {
++count_a_plus;
}
if (rdataA[karx] == (int)'0') {
++count_a_0;
}
if (rdataA[karx] == (int)'1') {
++count_a_1;
}
if (rdataA[karx] == (int)'2') {
++count_a_2;
}
if (rdataA[karx] == (int)'3') {
++count_a_3;
}
if (rdataA[karx] == (int)'4') {
++count_a_4;
}
if (rdataA[karx] == (int)'5') {
++count_a_5;
}
if (rdataA[karx] == (int)'6') {
++count_a_6;
}
if (rdataA[karx] == (int)'7') {
++count_a_7;
}
if (rdataA[karx] == (int)'8') {
++count_a_8;
}
if (rdataA[karx] == (int)'9') {
++count_a_9;
}
if (rdataA[karx] == (int)'A') {
++count_a_A;
}
if (rdataA[karx] == (int)'B') {
++count_a_B;
}
if (rdataA[karx] == (int)'C') {
++count_a_C;
}
if (rdataA[karx] == (int)'D') {
++count_a_D;
}
receive_a_char[karx] = (char)rdataA[karx];
}
SciaRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // Clear Overflow flag
SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack
}
interrupt void scibTxFifoIsr(void)
{
sdataB[0] = (int)'S';
sdataB[1] = (int)'+';
sdataB[2] = (int)'0';
sdataB[3] = (int)'1';
sdataB[4] = (int)'2';
sdataB[5] = (int)'3';
sdataB[6] = (int)'4';
sdataB[7] = (int)'5';
sdataB[8] = (int)'6';
sdataB[9] = (int)'7';
sdataB[10] = (int)'8';
sdataB[11] = (int)'9';
sdataB[12] = (int)'A';
sdataB[13] = (int)'B';
sdataB[14] = (int)'C';
sdataB[15] = (int)'D';
if (ScibRegs.SCIFFTX.bit.TXFFST == 0) {
Uint16 kb;
for(kb = 0; kb < 16; kb++) {
ScibRegs.SCITXBUF = sdataB[kb]; // Send data
}
}
send_b_count++;
ScibRegs.SCIFFTX.bit.TXFFINTCLR = 1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ACK
}
interrupt void scibRxFifoIsr(void)
{
Uint16 kbrx;
for (kbrx = 0; kbrx < 16 ; kbrx++) {
rdataB[kbrx] = ScibRegs.SCIRXBUF.all; // Read data
if (rdataB[kbrx] == (int)'S') {
++count_b_S;
}
if (rdataB[kbrx] == (int)'+') {
++count_b_plus;
}
if (rdataB[kbrx] == (int)'0') {
++count_b_0;
}
if (rdataB[kbrx] == (int)'1') {
++count_b_1;
}
if (rdataB[kbrx] == (int)'2') {
++count_b_2;
}
if (rdataB[kbrx] == (int)'3') {
++count_b_3;
}
if (rdataB[kbrx] == (int)'4') {
++count_b_4;
}
if (rdataB[kbrx] == (int)'5') {
++count_b_5;
}
if (rdataB[kbrx] == (int)'6') {
++count_b_6;
}
if (rdataB[kbrx] == (int)'7') {
++count_b_7;
}
if (rdataB[kbrx] == (int)'8') {
++count_b_8;
}
if (rdataB[kbrx] == (int)'9') {
++count_b_9;
}
if (rdataB[kbrx] == (int)'A') {
++count_b_A;
}
if (rdataB[kbrx] == (int)'B') {
++count_b_B;
}
if (rdataB[kbrx] == (int)'C') {
++count_b_C;
}
if (rdataB[kbrx] == (int)'D') {
++count_b_D;
}
receive_b_char[kbrx] = (char)rdataB[kbrx];
}
receive_b_count++;
ScibRegs.SCIFFRX.bit.RXFFOVRCLR = 1; // Clear Overflow flag
ScibRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack
}
void InitSciaGpio()
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.
//GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA)
//GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA)
GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up for GPIO35 (SCITXDA)
GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0; // Enable pull-up for GPIO36 (SCIRXDA)
/* Set qualification for selected pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
//GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA)
GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 3; // Asynch input GPIO36 (SCIRXDA)
/* Configure SCI-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SCI functional pins.
//GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation
//GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 1; // Configure GPIO35 for SCITXDA operation
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 1; // Configure GPIO36 for SCIRXDA operation
EDIS;
}
void InitScibGpio()
{
EALLOW;
/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
// For RealSys Board, use GPIO9 (SCITXDB) and GPIO11 (SCIRXDB)
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB)
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB)
// GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB)
/* Set qualification for selected pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB)
// GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB)
/* Configure SCI-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be SCI functional pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation
EDIS;
}
//===========================================================================
// No more.
//===========================================================================
How can I solve this? Is there any part of my code is wrong? Because the example program "Example_2833xSci_FFDLB_int." can run perfectly fine for both SCI-A and SCI-B (from which I derived my code).
I sincerely appreciate your time and assistance. Looking forward to your prompt response.
Kind regards,
Alif
