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Original question:

TMS320F28377D-EP: Access Arbitration scheme between CLA and CPU for the CLA/CPU MSGRAM

TMS320F280049C-Q1: Access Arbitration between CLA and CPU for the CpuToCla1MsgRAM.

JunYu Lai
Prodigy 10 points

Part Number: TMS320F280049C-Q1

Hello,

There is a question about reading and writing data from CpuToCla1MsgRAM.

What would happen during reading and writing a 32bits data combined with word#1 and word#2?

The CPU writes word #1 but right when the CPU finishes with word#1, the CLA wants to read words #1 and #2. Would CLA get word#1 with an updated value and word#2 with a stale value (from the previous cycle), or would the CLA be on hold until both words have been written by the CPU?

Thank you so much.

Leo

  • 0
    TI__Mastermind 32695 points

    Hi,

    Apologies for the delayed response. In your scenario, the application code should make sure there is sufficient delay added between the write and read to ensure the read gives the updated value. CLA core does not add delay cycles to protect the pipeline

    Regards,

    Veena