TMS320F28377S: How to use cycle by cycle trip for EPWM pulses in TMS320F28377S?

Hi Rupa,

Is this using an example from C2000Ware, and could you direct me to which example you are referring to?

Are you setting the TZSEL[CBC1] bit = 1 to enable a cycle-by-cycle trip for TZ1 and using TZA and TZB in the TZCTL register to select the actions desired for EPWM channels A and B? The cycle-by-cycle trip should be getting cleared every PWM cycle as specified with TZCLR[CBCPULSE]. What do you have selected for these bits? This should clear the trip if the trip event is no longer present.

You could also check that the CBC flag is getting set properly (TZFLG[CBC]) when TZ1 occurs.

Best Regards,

Allison

Hi Allison,

I am referring to this example code: C2000Ware_4_03_00_00\device_support\f2837xs\examples\cpu1\epwm_trip_zone. 

in the code the TZSEL[CBC1] bit is set to 1 and TZCTL.bit.TZA = TZ_FORCE_HI;

TZCLR[CBCPULSE] is not configured, should i configure that ?

This is the code snippet for your reference:

i modified the example code for epwm 8A (which was originally configured with epwm2A)
//
// Enable TZ1 as one cycle-by-cycle trip sources
//
EALLOW;
EPwm8Regs.TZSEL.bit.CBC1 = 1;

//
// Set TZA
//
EPwm8Regs.TZCTL.bit.TZA = TZ_FORCE_HI;

//
// Enable TZ interrupt
//
EPwm8Regs.TZEINT.bit.CBC = 1;
EDIS;

EPwm8Regs.TBPRD = 6000; // Set timer period
EPwm8Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm8Regs.TBCTR = 0x0000; // Clear counter

//
// Setup TBCLK
//
EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm8Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on
// the scope.

//
// Setup compare
//
EPwm8Regs.CMPA.bit.CMPA = 3000;

//
// Set actions
//
EPwm8Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on CAU
EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM2A on CAD

Hi Rupa,

The TZCLR[CBCPULSE] should be default set to clear the CBC trip latch when CTR=0, so that's ok (my only concern was if this was accidentally set to 11 where the CBC trip latch is not cleared). 

I see you are using EPWM8 registers- just wanted to also ask if you have tried just running the C2000Ware example without any modifications to verify that you can see the CBC trip function correctly on EPWM2? Then change it to EPWM8 after?

Best Regards,

Allison

Hi Allison,

As you said, i verified the C2000Ware example as it is with EPWM2 , but the CBC trip is not functioning correctly.

When TZ1 is pulled low, the PWM pulses remain high.

Hi Rupa,

These C2000Ware examples should be correct, so I will look deeper into it and test to see if there is perhaps a bug within the example on my end and will update you by end of Monday. In the meantime, one other thing you could try if you would like is downloading the latest version of C2000Ware (Version: 5.01.00.00) in case any changes were made between versions. I would also recommend looking at the DriverLib examples located at C2000Ware_5_01_00_00\driverlib\f2837xs\examples\cpu1\epwm. There are more examples there and there is a similar trip zone example there as well (but using DriverLib) to use - let me know if you are able to get this one to work!

Best Regards,

Allison

Hi Rupa,

I tested this out and the example epwm_trip_zone looks to be working as expected.

The TZ1 is initially tied high, meaning there is no trip (PWM functions normally). The trip condition will only be true when TZ1 signal is tied low; While the condition (TZ1 = low) is true, the CBC trip will keep repeating (cycle after cycle) and EPWM2 will remain high as a result of the trip until TZ1=high again (meaning the trip condition is no longer true). When I tie TZ1 high again, the CBC trip is no longer applicable and the PWM signal resumes as expected. Are you still seeing the EPWM2 signal stay high forever even when you tie TZ1 high again?

Best Regards,

Allison