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TMS320F28377D: Flash boot problem

Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

HI. 

I encountered a problem while testing an example in C2000ware.

The example I tested is the project named "ipc_ex4_msgqueue_sysconfig_multi" in the folder "C2000Ware_5_01_00_00\driverlib\f2837xd\examples\dual\ipc".

I imported the above project, set it to FLASH mode, and ran it.

When I download the program and run it while the XDS200 debugger is connected, it works normally.

However, when I disconnect the debugger and Reset the power, the boot does not work properly.

I saw a post about a similar problem on the "design support forums".

In the post, an engineer wrote that the following measures should be taken:


1. Please open your SysConfig GUI by clicking on either of the Sysconfig files in these projects, then scroll down until you see the CMD module. Open the CMD module, then scroll down to the 'C28x Compiler Sections' dropdown menu. Please change the codestart setting from 'Boot from RAMM' to 'Boot from Flash', and make sure to do this for both CPU1 and CPU2.

2. Next, as shown below, you will need to paste the following line just below Device_init() in your led_ex2_sysconfig_cpu1.c file:

Device_bootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);

I tried the above measures exactly as they were written, but the flashboot still does not work after resetting the power.

In the case of CMD, it is generated using a module supported by Sysconfig,

and the "predefined symbol" is added with "CMDTOOL" to apply it normally.

What part should I check?

  • Hi,

    Are you loading to both the cores. ? 

    When you import this example, it will create two projects in the workspace - one foe C28x1 core and one for C28x2 core. You need to compile both these projects, load the binaries generated to both the cores and then run the C28x1 core first, followed by the C28x2 core. 

    Best Regards

    Siddharth

  • Thanks for your answer.

    As you said, there are two projects for two cores, and two Binaries need to be downloaded. I am doing this through a multi-project.

    To be precise, when I import the project, three projects are automatically created.

    Two of them are for CPU 1/2, and the other one is a project that manages the two projects. And It's Name is a "Sysconfig_multi"

    When downloading using this project, the binary file is automatically downloaded to CPU1 and CPU2

    Then, CPU1 is first run, and CPU2 is run, and it works normally.

    The problem I want to mention is that the program does not work when the power is reset in this state.

    I think it should work normally even if the power is reset because it has been downloaded to Flash.

    The status of operation can be seen by checking the operation of the LED.

    the code that toggles the LED is placed in the While(1)  in Main Function.

  • Hi,

    Can you share the linker command files that are generated using SysConfig? 

    You can refer the led example 1 located at <C2000Ware>driverlib\f2837xd\examples\dual\led.  It has similar configuration details.  There is a build config for FLASH_Standalone for CPU1.  You can  refer the linker command file used in this example (2837xD_FLASH_lnk_cpu2.cmd)  and see if you have setup the code entry points correctly.

    Best Regards

    Siddharth

  • Thank you for your reply.

    First, I will upload the CMD file generated by Sysconfig in my project.

    I have copied the contents of the CMD file and moved it to a TXT file.

    As you explained, it is necessary to check if the code entry point is correct.

    As you can see from the CMD file I uploaded, "code start" is assigned to 0x80000 for both CPU1 and CPU2.

    I understand that this means the starting address when booting from Flash. I am not sure what the problem is just by looking at the CMD file.

    First, I will check if Dual Flash Boot works normally using the LED example you mentioned.

    I will let you know the results after checking.

    //
    // Active linker CMD configuration selected by 
    // the CMD Tool global settings
    //
    #define CMD0
    #ifdef CMD0
    
    MEMORY
    {
    
        RAMM0                     : origin = 0x000123, length = 0x0002DD
        RAMM1                     : origin = 0x000400, length = 0x0003F8
        CLATOCPU_MSGRAM           : origin = 0x001480, length = 0x000080
        CPUTOCLA_MSGRAM           : origin = 0x001500, length = 0x000080
        RAMLS0                    : origin = 0x008000, length = 0x000800
        RAMLS1                    : origin = 0x008800, length = 0x000800
        RAMLS2                    : origin = 0x009000, length = 0x000800
        RAMLS3                    : origin = 0x009800, length = 0x000800
        RAMLS4                    : origin = 0x00A000, length = 0x000800
        RAMLS5                    : origin = 0x00A800, length = 0x000800
        RAMD0                     : origin = 0x00B000, length = 0x000800
        RAMD1                     : origin = 0x00B800, length = 0x000800
        RAMGS0                    : origin = 0x00C000, length = 0x001000
        RAMGS1                    : origin = 0x00D000, length = 0x001000
        RAMGS2_3_4_5_6            : origin = 0x00E000, length = 0x005000
        RAMGS7                    : origin = 0x013000, length = 0x001000
        RAMGS8                    : origin = 0x014000, length = 0x001000
        RAMGS9                    : origin = 0x015000, length = 0x001000
        RAMGS10                   : origin = 0x016000, length = 0x001000
        RAMGS11                   : origin = 0x017000, length = 0x001000
        RAMGS12                   : origin = 0x018000, length = 0x001000
        RAMGS13                   : origin = 0x019000, length = 0x001000
        RAMGS14                   : origin = 0x01A000, length = 0x001000
        RAMGS15                   : origin = 0x01B000, length = 0x000FF8
        CPU2TOCPU1RAM             : origin = 0x03F800, length = 0x000400
        CPU1TOCPU2RAM             : origin = 0x03FC00, length = 0x000400
        FLASHA                    : origin = 0x080000, length = 0x002000
        FLASHB                    : origin = 0x082000, length = 0x002000
        FLASHC                    : origin = 0x084000, length = 0x002000
        FLASHD                    : origin = 0x086000, length = 0x002000
        FLASHE                    : origin = 0x088000, length = 0x008000
        FLASHF                    : origin = 0x090000, length = 0x008000
        FLASHG                    : origin = 0x098000, length = 0x008000
        FLASHH                    : origin = 0x0A0000, length = 0x008000
        FLASHI                    : origin = 0x0A8000, length = 0x008000
        FLASHJ                    : origin = 0x0B0000, length = 0x008000
        FLASHK_L_M                : origin = 0x0B8000, length = 0x006000
        FLASHN                    : origin = 0x0BE000, length = 0x001FF0
        RESET                     : origin = 0x3FFFC0, length = 0x000002
    }
    
    
    SECTIONS
    {
        //
        // C28x Sections
        //
        .reset               : >  RESET, TYPE = DSECT /* not used, */
        codestart            : >  0x080000
        .text                : >> FLASHB | FLASHC | FLASHD | FLASHE,
                                  ALIGN(8)
        .TI.ramfunc          :    LOAD >  FLASHK_L_M,
                                  RUN  >  RAMGS2_3_4_5_6,
                                  TABLE(BINIT),
                                  ALIGN(8)
        .binit               : >  FLASHA,
                                  ALIGN(8)
        .ovly                : >  FLASHA,
                                  ALIGN(8)
        .cinit               : >  FLASHA,
                                  ALIGN(8)
        .stack               : >  RAMM1
        .init_array          : >  FLASHB,
                                  ALIGN(8)
        .bss                 : >  RAMLS5
        .const               : >  FLASHF,
                                  ALIGN(8)
        .data                : >  RAMLS5
        .switch              : >  FLASHA,
                                  ALIGN(8)
        .sysmem              : >  RAMLS5
        MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
        MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
    
    }
    
    #endif
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    
    //
    // Active linker CMD configuration selected by 
    // the CMD Tool global settings
    //
    #define CMD0
    #ifdef CMD0
    
    MEMORY
    {
    
        RAMM0                     : origin = 0x0000A2, length = 0x00035E
        RAMM1                     : origin = 0x000400, length = 0x0003F8
        CLATOCPU_MSGRAM           : origin = 0x001480, length = 0x000080
        CPUTOCLA_MSGRAM           : origin = 0x001500, length = 0x000080
        RAMLS0                    : origin = 0x008000, length = 0x000800
        RAMLS1                    : origin = 0x008800, length = 0x000800
        RAMLS2                    : origin = 0x009000, length = 0x000800
        RAMLS3                    : origin = 0x009800, length = 0x000800
        RAMLS4                    : origin = 0x00A000, length = 0x000800
        RAMLS5                    : origin = 0x00A800, length = 0x000800
        RAMD0                     : origin = 0x00B000, length = 0x000800
        RAMD1                     : origin = 0x00B800, length = 0x000800
        RAMGS0                    : origin = 0x00C000, length = 0x001000
        RAMGS1                    : origin = 0x00D000, length = 0x001000
        RAMGS2                    : origin = 0x00E000, length = 0x001000
        RAMGS3                    : origin = 0x00F000, length = 0x001000
        RAMGS4                    : origin = 0x010000, length = 0x001000
        RAMGS5                    : origin = 0x011000, length = 0x001000
        RAMGS6                    : origin = 0x012000, length = 0x001000
        RAMGS7                    : origin = 0x013000, length = 0x001000
        RAMGS8                    : origin = 0x014000, length = 0x001000
        RAMGS9                    : origin = 0x015000, length = 0x001000
        RAMGS10                   : origin = 0x016000, length = 0x001000
        RAMGS11                   : origin = 0x017000, length = 0x001000
        RAMGS12                   : origin = 0x018000, length = 0x001000
        RAMGS13                   : origin = 0x019000, length = 0x001000
        RAMGS14                   : origin = 0x01A000, length = 0x001000
        RAMGS15                   : origin = 0x01B000, length = 0x000FF8
        CPU2TOCPU1RAM             : origin = 0x03F800, length = 0x000400
        CPU1TOCPU2RAM             : origin = 0x03FC00, length = 0x000400
        FLASHA                    : origin = 0x080000, length = 0x002000
        FLASHB                    : origin = 0x082000, length = 0x002000
        FLASHC                    : origin = 0x084000, length = 0x002000
        FLASHD                    : origin = 0x086000, length = 0x002000
        FLASHE                    : origin = 0x088000, length = 0x008000
        FLASHF                    : origin = 0x090000, length = 0x008000
        FLASHG                    : origin = 0x098000, length = 0x008000
        FLASHH                    : origin = 0x0A0000, length = 0x008000
        FLASHI                    : origin = 0x0A8000, length = 0x008000
        FLASHJ                    : origin = 0x0B0000, length = 0x008000
        FLASHK                    : origin = 0x0B8000, length = 0x002000
        FLASHL                    : origin = 0x0BA000, length = 0x002000
        FLASHM                    : origin = 0x0BC000, length = 0x002000
        FLASHN                    : origin = 0x0BE000, length = 0x001FF0
        RESET                     : origin = 0x3FFFC0, length = 0x000002
    }
    
    
    SECTIONS
    {
        //
        // C28x Sections
        //
        .reset               : >  RESET, TYPE = DSECT /* not used, */
        codestart            : >  0x080000
        .text                : >> FLASHB | FLASHC | FLASHD | FLASHE,
                                  ALIGN(8)
        .TI.ramfunc          :    LOAD >  FLASHD,
                                  RUN  >  RAMLS0,
                                  TABLE(BINIT),
                                  ALIGN(8)
        .binit               : >  FLASHA,
                                  ALIGN(8)
        .ovly                : >  FLASHA,
                                  ALIGN(8)
        .cinit               : >  FLASHA,
                                  ALIGN(8)
        .stack               : >  RAMM1
        .init_array          : >  FLASHB,
                                  ALIGN(8)
        .bss                 : >  RAMLS5
        .const               : >  FLASHF,
                                  ALIGN(8)
        .data                : >  RAMLS5
        .switch              : >  FLASHA,
                                  ALIGN(8)
        .sysmem              : >  RAMLS5
        MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
        MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
    
    }
    
    #endif
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

  • Hi, 

    Will take a look at these files and get back to you.  Let me know if you are able to run the LED example. 

    Best Regards

    Siddharth

  • I have tried the LED example you mentioned.

    Dual Core Flash Boot was successful, and the application also ran normally. \

    So, I am gradually transferring the project I am currently working on to the LED project.

    However, I still do not know what the problem is with the project I used in the past.

    Even when I compare the CMD file with the one in the LED project, I cannot see the problem.

    I have also tried to change the CMD file in the LED project to be similar to the settings of the project I am currently working on, but it still works well.

    In any case, since the LED project is not a problem,

    I think there will be no problem in proceeding for the time being.

    Thank you.