TMS320F28388D: CPU2 cannot detect ADC interrupt

Fabio Rastrello

Part Number: TMS320F28388D
Other Parts Discussed in Thread: SYSCONFIG

Hi,

I have perfectly the same issue, but it is not clear for me how to fix it.

I am using SysConfig in CPU1 to configure ADCA and ADCB, ePWM1/2/6/7/8/ and ADCA/B Interrupts, but I need to manage ADCA interrupt in CPU1 and ADCB interrupt in CPU2. The same ISR is entered if everything is in CPU1, it is not entered if it is in CPU2.

This is my code in CPU2 main and the related ISR.

    ...
    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    // Interrupt Settings for INT_ADCB1
    Interrupt_register(INT_ADCB1, &INT_ADC_VR_ISR);
    Interrupt_enable(INT_ADCB1);
    
    ...
    
    
void INT_ADC_VR_ISR(void){
    //
    // Clear the interrupt flag
    ADC_clearInterruptStatus(ADC_B_BASE, ADC_INT_NUMBER1);

    //
    // Check if overflow has occurred
    if(true == ADC_getInterruptOverflowStatus(ADC_B_BASE, ADC_INT_NUMBER1))
    {
        ADC_clearInterruptOverflowStatus(ADC_B_BASE, ADC_INT_NUMBER1);
        ADC_clearInterruptStatus(ADC_B_BASE, ADC_INT_NUMBER1);
    }

    //
    // Acknowledge the interrupt
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}

What am I missing tin order to trigger correctly the interrupt in CPU2?

Thanks ,

Fabio

over 1 year ago

0 Vivek Singh over 1 year ago

TI__Guru** 115231 points

Fabio,

On CPU2, are other interrupts working fine and issue is only with ADCB ? Asking this to make sure there is no issue with general interrupt setup on CPU2

Vivek Singh

0 Fabio Rastrello over 1 year ago in reply to Vivek Singh

Prodigy 120 points

Hi Vivek,

I have only that interrupt configured in CPU2.

By the way, I tried to configure a TIMER0 with interrupt in this way:

...
//CPU2 TIMER0 for VR control Task
CPUTimer_setEmulationMode(CPUTIMER0_BASE, CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT);
CPUTimer_setPreScaler(CPUTIMER0_BASE, 0U);
CPUTimer_setPeriod(CPUTIMER0_BASE, 4000U);
CPUTimer_enableInterrupt(CPUTIMER0_BASE);
CPUTimer_stopTimer(CPUTIMER0_BASE);

CPUTimer_reloadTimerCounter(CPUTIMER0_BASE);
CPUTimer_startTimer(CPUTIMER0_BASE);

Interrupt_register(INT_TIMER0, &INT_VR_Timer_ISR);
Interrupt_enable(INT_TIMER0);

...

void INT_VR_Timer_ISR(void){
    counter++;

    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}

and everything works fine.

Returning to my issue, I want to clarify that my architecture is this: the EPWM6 triggers the SOC6 of ADCB, and the related EOC launches the interrupt. Everything configured with SysConfig in CPU1.

My doubt is, like user6301164 already said in linked question: "When i configure the pwm1 interrupt in the CPU1 and CPU2, both of them can enter the pwm1 interrupt. "

In fact, if I register the same interrupt about ADC in CPU1 in this way:

It is correctly trigger by both CPU1 and CPU2, but I cannot find a way to avoid the interrupt configuration in CPU1 and configure and use it only in CPU2. Or is it the correct way to manage it? I can leave the CPU1 interrupt empty with just aknowledge it, but it is a sort of workaround for me.

Moreover, to be clear, the flag "Use Interrupt" is always selected, both when I register and use it only in CPU2 (interrupt KO) and when I register and use in both cores (interrupt OK).

Thanks again,

Fabio

0 Ibukun Olumuyiwa over 1 year ago in reply to Fabio Rastrello

TI__Genius 11011 points

Hello Fabio,

If you intend to use ADCB in CPU2, then you should configure the CPU ownership accordingly. In SysConfig, under SYSCTL, assign ADCB to CPU2.

If you wish to do this in code, the function call is:

    // Assign ADCB to CPU2
    SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL11_ADC, 2, SYSCTL_CPUSEL_CPU2);

Best regards,
Ibukun

0 Fabio Rastrello over 1 year ago in reply to Ibukun Olumuyiwa

Prodigy 120 points

Hi Ibukun,

thanks a lot, I'm not using the SYSCTL menu in SysConfig, so I assigned ADCB to CPU2 in code as you suggeted (after Board_Init()), but in this way ADCB interrupt is entered only in CPU1 (if it is registered in that core), never in CPU2.

I tried also to add:

SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_EPWM6, SYSCTL_CPUSEL_CPU2);

To assign also EPWM6 to CPU2 (that actually will be updated in that core), with no success.

Something else is missing?

Thanks again,

Fabio

0 Ibukun Olumuyiwa over 1 year ago in reply to Fabio Rastrello

TI__Genius 11011 points

Fabio,

Just to clarify, are you trying to have both CPU1 and CPU2 respond to ADCB interrupts? Each CPU has its own PIE module, so if you want both CPUs to respond to ADCB's interrupt signal, then you must independently configure the PIE modules on both CPU1 and CPU2 to respond to it. For more details, please take a look at the device technical reference manual, section 3.4 - Peripheral Interrupts.

Best regards,
Ibukun

0 Fabio Rastrello over 1 year ago in reply to Ibukun Olumuyiwa

Prodigy 120 points

Hi Ibukun

thanks again, but what is happening with this initialization:

Fabio Rastrello said:
This is my code in CPU2 main and the related ISR.
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...
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
Interrupt_initModule();
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
Interrupt_initVectorTable();
// Interrupt Settings for INT_ADCB1
Interrupt_register(INT_ADCB1, &INT_ADC_VR_ISR);
Interrupt_enable(INT_ADCB1);

...

void INT_ADC_VR_ISR(void){
//
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    ...
    //
    // Initialize PIE and clear PIE registers. Disables CPU interrupts.
    //
    Interrupt_initModule();

    //
    // Initialize the PIE vector table with pointers to the shell Interrupt
    // Service Routines (ISR).
    //
    Interrupt_initVectorTable();

    // Interrupt Settings for INT_ADCB1
    Interrupt_register(INT_ADCB1, &INT_ADC_VR_ISR);
    Interrupt_enable(INT_ADCB1);
    
    ...
    
    
void INT_ADC_VR_ISR(void){
    //
    // Clear the interrupt flag
    ADC_clearInterruptStatus(ADC_B_BASE, ADC_INT_NUMBER1);

    //
    // Check if overflow has occurred
    if(true == ADC_getInterruptOverflowStatus(ADC_B_BASE, ADC_INT_NUMBER1))
    {
        ADC_clearInterruptOverflowStatus(ADC_B_BASE, ADC_INT_NUMBER1);
        ADC_clearInterruptStatus(ADC_B_BASE, ADC_INT_NUMBER1);
    }

    //
    // Acknowledge the interrupt
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP1);
}
    
    
What am I missing tin order to trigger correctly the interrupt in CPU2?

is that I can trigger ADC interrupt in this way:

- Only in CPU1 -> OK

- Both CPU1 and CPU2 -> OK

- Only CPU2 -> KO

It seems I cannot have only ADC CPU2 interrupt without having also ADC CPU1 interrupt.

Thanks,

Fabio

0 Ibukun Olumuyiwa over 1 year ago in reply to Fabio Rastrello

TI__Genius 11011 points

Fabio,

Do you have EINT and ERTM in your CPU2 main function?

Thanks,
Ibukun

0 Fabio Rastrello over 1 year ago in reply to Ibukun Olumuyiwa

Prodigy 120 points

Yes, of course, at the end of overall initializations:

    //
    // Clear any IPC flags if set already
    IPC_clearFlagLtoR(IPC_CPU2_L_CPU1_R, IPC_FLAG_ALL);
    // Synchronize both the cores.
    IPC_sync(IPC_CPU2_L_CPU1_R, IPC_FLAG31);

    //
    // Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
    //
    EINT;
    ERTM;

if not I think I could not have this:

Fabio Rastrello said:
- Both CPU1 and CPU2 -> OK

Thanks,

Fabio

0 Ibukun Olumuyiwa over 1 year ago in reply to Fabio Rastrello

TI__Genius 11011 points

Hello Fabio,

Sorry for the delayed response. I am consulting with our system control experts to get some more insight into your issue.

Best regards,
Ibukun

0 Fabio Rastrello over 1 year ago in reply to Ibukun Olumuyiwa

Prodigy 120 points

Hi Ibukun,

do you have any update about this topic? I'm still managing the ADC interrupt in both cores in order to have it in CPU2: it is not a big issue to manage it in both cores, but I'm concerned about performances of my code that could beaffected considering some very fast control operations.

Thanks again and best regrds,

Fabio

0 Ibukun Olumuyiwa over 1 year ago in reply to Fabio Rastrello

TI__Genius 11011 points

Hello Fabio,

So far it seems like you've configured everything correctly. Can we see the output in board.c for when you set it up for CPU1+CPU2 and it works, versus when you configure it for CPU2 only? I'm wondering if a diff of the generated code can give us a clue as to why the CPU2 only case does not work.

Best regards,
Ibukun

0 Fabio Rastrello over 1 year ago in reply to Ibukun Olumuyiwa

Prodigy 120 points

Hi Ibukun,

when I don't register the interrupt with SysConfig in CPU1:

this is the board.c code:

/*
 * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include "board.h"

//*****************************************************************************
//
// Board Configurations
// Initializes the rest of the modules. 
// Call this function in your application if you wish to do all module 
// initialization.
// If you wish to not use some of the initializations, instead of the 
// Board_init use the individual Module_inits
//
//*****************************************************************************
void Board_init()
{
	EALLOW;

	PinMux_init();
	SYNC_init();
	ADC_init();
	DMA_init();
	EPWM_init();
	GPIO_init();
	SPI_init();
	INTERRUPT_init();

	EDIS;
}

//*****************************************************************************
//
// PINMUX Configurations
//
//*****************************************************************************
void PinMux_init()
{
	//
	// PinMux for modules assigned to CPU1
	//
	
	//
	// EPWM1 -> HB_A Pinmux
	//
	GPIO_setPinConfig(HB_A_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(HB_A_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_A_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(HB_A_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(HB_A_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_A_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM2 -> HB_B Pinmux
	//
	GPIO_setPinConfig(HB_B_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(HB_B_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_B_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(HB_B_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(HB_B_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_B_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM6 -> VR_A Pinmux
	//
	GPIO_setPinConfig(VR_A_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(VR_A_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_A_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(VR_A_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(VR_A_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_A_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM7 -> VR_B Pinmux
	//
	GPIO_setPinConfig(VR_B_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(VR_B_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_B_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(VR_B_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(VR_B_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_B_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM8 -> VR_C Pinmux
	//
	GPIO_setPinConfig(VR_C_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(VR_C_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_C_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(VR_C_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(VR_C_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_C_EPWMB_GPIO, GPIO_QUAL_SYNC);

	// GPIO31 -> LED1_MCU1_GPIO Pinmux
	GPIO_setPinConfig(GPIO_31_GPIO31);
	// GPIO34 -> LED2_MCU1_GPIO Pinmux
	GPIO_setPinConfig(GPIO_34_GPIO34);
	// GPIO67 -> DI6_ME Pinmux
	GPIO_setPinConfig(GPIO_67_GPIO67);
	// GPIO36 -> DIO4 Pinmux
	GPIO_setPinConfig(GPIO_36_GPIO36);
	// GPIO37 -> DIO5 Pinmux
	GPIO_setPinConfig(GPIO_37_GPIO37);
	// GPIO38 -> DIO6 Pinmux
	GPIO_setPinConfig(GPIO_38_GPIO38);
	// GPIO39 -> DIO7 Pinmux
	GPIO_setPinConfig(GPIO_39_GPIO39);
	// GPIO40 -> DIO8 Pinmux
	GPIO_setPinConfig(GPIO_40_GPIO40);
	// GPIO41 -> DIO9 Pinmux
	GPIO_setPinConfig(GPIO_41_GPIO41);
	// GPIO49 -> FLT_ZVS_HBA Pinmux
	GPIO_setPinConfig(GPIO_49_GPIO49);
	// GPIO50 -> FLT_ZVS_HBB Pinmux
	GPIO_setPinConfig(GPIO_50_GPIO50);
	// GPIO55 -> IN_DIO1 Pinmux
	GPIO_setPinConfig(GPIO_55_GPIO55);
	// GPIO56 -> IN_DIO2 Pinmux
	GPIO_setPinConfig(GPIO_56_GPIO56);
	// GPIO57 -> IN_DIO3 Pinmux
	GPIO_setPinConfig(GPIO_57_GPIO57);
	// GPIO58 -> IN_DIO4 Pinmux
	GPIO_setPinConfig(GPIO_58_GPIO58);
	// GPIO59 -> IN_DIO5 Pinmux
	GPIO_setPinConfig(GPIO_59_GPIO59);
	//
	// SPIB -> SPI_MCU2 Pinmux
	//
	GPIO_setPinConfig(SPI_MCU2_SPIPICO_PIN_CONFIG);
	GPIO_setPadConfig(SPI_MCU2_SPIPICO_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_MCU2_SPIPICO_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_MCU2_SPIPOCI_PIN_CONFIG);
	GPIO_setPadConfig(SPI_MCU2_SPIPOCI_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_MCU2_SPIPOCI_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_MCU2_SPICLK_PIN_CONFIG);
	GPIO_setPadConfig(SPI_MCU2_SPICLK_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_MCU2_SPICLK_GPIO, GPIO_QUAL_ASYNC);

	//
	// SPID -> SPI_FPGA Pinmux
	//
	GPIO_setPinConfig(SPI_FPGA_SPIPICO_PIN_CONFIG);
	GPIO_setPadConfig(SPI_FPGA_SPIPICO_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_FPGA_SPIPICO_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_FPGA_SPIPOCI_PIN_CONFIG);
	GPIO_setPadConfig(SPI_FPGA_SPIPOCI_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_FPGA_SPIPOCI_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_FPGA_SPICLK_PIN_CONFIG);
	GPIO_setPadConfig(SPI_FPGA_SPICLK_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_FPGA_SPICLK_GPIO, GPIO_QUAL_ASYNC);


}

//*****************************************************************************
//
// ADC Configurations
//
//*****************************************************************************
void ADC_init(){
	ADC_B_init();
	ADC_A_init();
}

void ADC_B_init(){
	//
	// ADC Initialization: Write ADC configurations and power up the ADC
	//
	// Configures the analog-to-digital converter module prescaler.
	//
	ADC_setPrescaler(ADC_B_BASE, ADC_CLK_DIV_4_0);
	//
	// Configures the analog-to-digital converter resolution and signal mode.
	//
	ADC_setMode(ADC_B_BASE, ADC_RESOLUTION_12BIT, ADC_MODE_SINGLE_ENDED);
	//
	// Sets the timing of the end-of-conversion pulse
	//
	ADC_setInterruptPulseMode(ADC_B_BASE, ADC_PULSE_END_OF_CONV);
	//
	// Powers up the analog-to-digital converter core.
	//
	ADC_enableConverter(ADC_B_BASE);
	//
	// Delay for 1ms to allow ADC time to power up
	//
	DEVICE_DELAY_US(500);
	//
	// SOC Configuration: Setup ADC EPWM channel and trigger settings
	//
	// Disables SOC burst mode.
	//
	ADC_disableBurstMode(ADC_B_BASE);
	//
	// Sets the priority mode of the SOCs.
	//
	ADC_setSOCPriority(ADC_B_BASE, ADC_PRI_ALL_ROUND_ROBIN);
	//
	// Start of Conversion 0 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 0
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN0
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_B_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN0, 15U);
	ADC_setInterruptSOCTrigger(ADC_B_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 1 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 1
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_B_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(ADC_B_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 2 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 2
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN2
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_B_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN2, 15U);
	ADC_setInterruptSOCTrigger(ADC_B_BASE, ADC_SOC_NUMBER2, ADC_INT_SOC_TRIGGER_NONE);
	//
	// ADC Interrupt 1 Configuration
	// 		Source	: ADC_SOC_NUMBER0
	// 		Interrupt Source: enabled
	// 		Continuous Mode	: disabled
	//
	//
	ADC_setInterruptSource(ADC_B_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER0);
	ADC_clearInterruptStatus(ADC_B_BASE, ADC_INT_NUMBER1);
	ADC_disableContinuousMode(ADC_B_BASE, ADC_INT_NUMBER1);
	ADC_enableInterrupt(ADC_B_BASE, ADC_INT_NUMBER1);
}
void ADC_A_init(){
	//
	// ADC Initialization: Write ADC configurations and power up the ADC
	//
	// Configures the analog-to-digital converter module prescaler.
	//
	ADC_setPrescaler(ADC_A_BASE, ADC_CLK_DIV_4_0);
	//
	// Configures the analog-to-digital converter resolution and signal mode.
	//
	ADC_setMode(ADC_A_BASE, ADC_RESOLUTION_12BIT, ADC_MODE_SINGLE_ENDED);
	//
	// Sets the timing of the end-of-conversion pulse
	//
	ADC_setInterruptPulseMode(ADC_A_BASE, ADC_PULSE_END_OF_CONV);
	//
	// Powers up the analog-to-digital converter core.
	//
	ADC_enableConverter(ADC_A_BASE);
	//
	// Delay for 1ms to allow ADC time to power up
	//
	DEVICE_DELAY_US(500);
	//
	// SOC Configuration: Setup ADC EPWM channel and trigger settings
	//
	// Disables SOC burst mode.
	//
	ADC_disableBurstMode(ADC_A_BASE);
	//
	// Sets the priority mode of the SOCs.
	//
	ADC_setSOCPriority(ADC_A_BASE, ADC_PRI_ALL_ROUND_ROBIN);
	//
	// Start of Conversion 0 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 0
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN14
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN14, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 1 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 1
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN15
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN15, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 2 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 2
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER2, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 3 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 3
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN2
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN2, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER3, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 4 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 4
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN3
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER4, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN3, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER4, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 5 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 5
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER5, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 20U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER5, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 6 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 6
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN5
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER6, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN5, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER6, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 8 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 8
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER8, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER8, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 9 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 9
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER9, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER9, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 10 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 10
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER10, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER10, ADC_INT_SOC_TRIGGER_NONE);
	//
	// ADC Interrupt 1 Configuration
	// 		Source	: ADC_SOC_NUMBER5
	// 		Interrupt Source: enabled
	// 		Continuous Mode	: disabled
	//
	//
	ADC_setInterruptSource(ADC_A_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER5);
	ADC_clearInterruptStatus(ADC_A_BASE, ADC_INT_NUMBER1);
	ADC_disableContinuousMode(ADC_A_BASE, ADC_INT_NUMBER1);
	ADC_enableInterrupt(ADC_A_BASE, ADC_INT_NUMBER1);
}


//*****************************************************************************
//
// DMA Configurations
//
//*****************************************************************************
void DMA_init(){
    DMA_initController();
	SPI_MCU2_TX_DMA_init();
	SPI_MCU2_RX_DMA_init();
	SPI_FPGA_RX_DMA_init();
	SPI_FPGA_TX_DMA_init();
}

void SPI_MCU2_TX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_STOP);
    DMA_configAddresses(SPI_MCU2_TX_DMA_BASE, SPI_MCU2_TX_DMA_ADDRESS, dma1TxAddr);
    DMA_configBurst(SPI_MCU2_TX_DMA_BASE, 8U, 1, 0);
    DMA_configTransfer(SPI_MCU2_TX_DMA_BASE, 8U, 1, 0);
    DMA_configWrap(SPI_MCU2_TX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_MCU2_TX_DMA_BASE, SPI_MCU2_TX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_MCU2_TX_DMA_BASE);
    DMA_stopChannel(SPI_MCU2_TX_DMA_BASE);
}
void SPI_MCU2_RX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_STOP);
    DMA_configAddresses(SPI_MCU2_RX_DMA_BASE, dma2RxAddr, SPI_MCU2_RX_DMA_ADDRESS);
    DMA_configBurst(SPI_MCU2_RX_DMA_BASE, 8U, 0, 1);
    DMA_configTransfer(SPI_MCU2_RX_DMA_BASE, 8U, 0, 1);
    DMA_configWrap(SPI_MCU2_RX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_MCU2_RX_DMA_BASE, SPI_MCU2_RX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_MCU2_RX_DMA_BASE);
    DMA_stopChannel(SPI_MCU2_RX_DMA_BASE);
}
void SPI_FPGA_RX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_FREE_RUN);
    DMA_configAddresses(SPI_FPGA_RX_DMA_BASE, dma4RxAddr, SPI_FPGA_RX_DMA_ADDRESS);
    DMA_configBurst(SPI_FPGA_RX_DMA_BASE, 10U, 0, 1);
    DMA_configTransfer(SPI_FPGA_RX_DMA_BASE, 5U, 0, 1);
    DMA_configWrap(SPI_FPGA_RX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_FPGA_RX_DMA_BASE, SPI_FPGA_RX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_FPGA_RX_DMA_BASE);
    DMA_stopChannel(SPI_FPGA_RX_DMA_BASE);
}
void SPI_FPGA_TX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_STOP);
    DMA_configAddresses(SPI_FPGA_TX_DMA_BASE, SPI_FPGA_TX_DMA_ADDRESS, dma3TxAddr);
    DMA_configBurst(SPI_FPGA_TX_DMA_BASE, 5U, 1, 0);
    DMA_configTransfer(SPI_FPGA_TX_DMA_BASE, 10U, 1, 0);
    DMA_configWrap(SPI_FPGA_TX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_FPGA_TX_DMA_BASE, SPI_FPGA_TX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_FPGA_TX_DMA_BASE);
    DMA_stopChannel(SPI_FPGA_TX_DMA_BASE);
}

//*****************************************************************************
//
// EPWM Configurations
//
//*****************************************************************************
void EPWM_init(){
    EPWM_enableGlobalLoad(HB_A_BASE);	
    EPWM_setGlobalLoadEventPrescale(HB_A_BASE, 1);	
    EPWM_setEmulationMode(HB_A_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(HB_A_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(HB_A_BASE, 999);	
    EPWM_setTimeBaseCounter(HB_A_BASE, 0);	
    EPWM_setTimeBaseCounterMode(HB_A_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(HB_A_BASE);	
    EPWM_setPhaseShift(HB_A_BASE, 1);	
    EPWM_enableSyncOutPulseSource(HB_A_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(HB_A_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(HB_A_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_A_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(HB_A_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_A_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(HB_A_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(HB_A_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(HB_A_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(HB_A_BASE, 10);	
    EPWM_setDeadBandDelayMode(HB_A_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(HB_A_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(HB_A_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(HB_A_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(HB_A_BASE);	
    EPWM_enableADCTrigger(HB_A_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(HB_A_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(HB_A_BASE, EPWM_SOC_A, 1);	
    EPWM_enableGlobalLoad(HB_B_BASE);	
    EPWM_setGlobalLoadEventPrescale(HB_B_BASE, 1);	
    EPWM_setEmulationMode(HB_B_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(HB_B_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(HB_B_BASE, 999);	
    EPWM_setupEPWMLinks(HB_B_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(HB_B_BASE, 0);	
    EPWM_setTimeBaseCounterMode(HB_B_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(HB_B_BASE);	
    EPWM_setPhaseShift(HB_B_BASE, 1);	
    EPWM_enableSyncOutPulseSource(HB_B_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(HB_B_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(HB_B_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_B_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(HB_B_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_B_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(HB_B_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(HB_B_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(HB_B_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(HB_B_BASE, 10);	
    EPWM_setDeadBandDelayMode(HB_B_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(HB_B_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(HB_B_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(HB_B_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(HB_B_BASE);	
    EPWM_enableGlobalLoad(VR_A_BASE);	
    EPWM_setGlobalLoadEventPrescale(VR_A_BASE, 1);	
    EPWM_setEmulationMode(VR_A_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(VR_A_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(VR_A_BASE, 999);	
    EPWM_setupEPWMLinks(VR_A_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(VR_A_BASE, 0);	
    EPWM_setTimeBaseCounterMode(VR_A_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(VR_A_BASE);	
    EPWM_setPhaseShift(VR_A_BASE, 1);	
    EPWM_enableSyncOutPulseSource(VR_A_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(VR_A_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(VR_A_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_A_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(VR_A_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_A_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(VR_A_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(VR_A_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(VR_A_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(VR_A_BASE, 10);	
    EPWM_setDeadBandDelayMode(VR_A_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(VR_A_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(VR_A_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(VR_A_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(VR_A_BASE);	
    EPWM_enableADCTrigger(VR_A_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(VR_A_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(VR_A_BASE, EPWM_SOC_A, 1);	
    EPWM_enableGlobalLoad(VR_B_BASE);	
    EPWM_setGlobalLoadEventPrescale(VR_B_BASE, 1);	
    EPWM_setEmulationMode(VR_B_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(VR_B_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(VR_B_BASE, 999);	
    EPWM_setupEPWMLinks(VR_B_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(VR_B_BASE, 0);	
    EPWM_setTimeBaseCounterMode(VR_B_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(VR_B_BASE);	
    EPWM_setPhaseShift(VR_B_BASE, 1);	
    EPWM_enableSyncOutPulseSource(VR_B_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(VR_B_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(VR_B_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_B_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(VR_B_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_B_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(VR_B_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(VR_B_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(VR_B_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(VR_B_BASE, 10);	
    EPWM_setDeadBandDelayMode(VR_B_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(VR_B_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(VR_B_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(VR_B_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(VR_B_BASE);	
    EPWM_enableGlobalLoad(VR_C_BASE);	
    EPWM_setGlobalLoadEventPrescale(VR_C_BASE, 1);	
    EPWM_setEmulationMode(VR_C_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(VR_C_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(VR_C_BASE, 999);	
    EPWM_setupEPWMLinks(VR_C_BASE, EPWM_LINK_WITH_EPWM_6, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(VR_C_BASE, 0);	
    EPWM_setTimeBaseCounterMode(VR_C_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(VR_C_BASE);	
    EPWM_setPhaseShift(VR_C_BASE, 1);	
    EPWM_enableSyncOutPulseSource(VR_C_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(VR_C_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(VR_C_BASE, EPWM_COUNTER_COMPARE_A, 400);	
    EPWM_setCounterCompareShadowLoadMode(VR_C_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(VR_C_BASE, EPWM_COUNTER_COMPARE_B, 600);	
    EPWM_setCounterCompareShadowLoadMode(VR_C_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(VR_C_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(VR_C_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(VR_C_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(VR_C_BASE, 10);	
    EPWM_setDeadBandDelayMode(VR_C_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(VR_C_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(VR_C_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(VR_C_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(VR_C_BASE);	
    EPWM_enableADCTrigger(VR_C_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(VR_C_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(VR_C_BASE, EPWM_SOC_A, 1);	
}

//*****************************************************************************
//
// GPIO Configurations
//
//*****************************************************************************
void GPIO_init(){
	LED1_MCU1_GPIO_init();
	LED2_MCU1_GPIO_init();
	DI6_ME_init();
	DIO4_init();
	DIO5_init();
	DIO6_init();
	DIO7_init();
	DIO8_init();
	DIO9_init();
	FLT_ZVS_HBA_init();
	FLT_ZVS_HBB_init();
	IN_DIO1_init();
	IN_DIO2_init();
	IN_DIO3_init();
	IN_DIO4_init();
	IN_DIO5_init();
}

void LED1_MCU1_GPIO_init(){
	GPIO_writePin(LED1_MCU1_GPIO, 1);
	GPIO_setPadConfig(LED1_MCU1_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(LED1_MCU1_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(LED1_MCU1_GPIO, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(LED1_MCU1_GPIO, GPIO_CORE_CPU1);
}
void LED2_MCU1_GPIO_init(){
	GPIO_writePin(LED2_MCU1_GPIO, 1);
	GPIO_setPadConfig(LED2_MCU1_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(LED2_MCU1_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(LED2_MCU1_GPIO, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(LED2_MCU1_GPIO, GPIO_CORE_CPU2);
}
void DI6_ME_init(){
	GPIO_setPadConfig(DI6_ME, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DI6_ME, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DI6_ME, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(DI6_ME, GPIO_CORE_CPU1);
}
void DIO4_init(){
	GPIO_writePin(DIO4, 0);
	GPIO_setPadConfig(DIO4, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO4, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO4, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO4, GPIO_CORE_CPU1);
}
void DIO5_init(){
	GPIO_writePin(DIO5, 0);
	GPIO_setPadConfig(DIO5, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO5, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO5, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO5, GPIO_CORE_CPU1);
}
void DIO6_init(){
	GPIO_writePin(DIO6, 0);
	GPIO_setPadConfig(DIO6, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO6, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO6, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO6, GPIO_CORE_CPU2);
}
void DIO7_init(){
	GPIO_writePin(DIO7, 0);
	GPIO_setPadConfig(DIO7, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO7, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO7, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO7, GPIO_CORE_CPU2);
}
void DIO8_init(){
	GPIO_setPadConfig(DIO8, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO8, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO8, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(DIO8, GPIO_CORE_CPU1);
}
void DIO9_init(){
	GPIO_setPadConfig(DIO9, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO9, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO9, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(DIO9, GPIO_CORE_CPU1);
}
void FLT_ZVS_HBA_init(){
	GPIO_setPadConfig(FLT_ZVS_HBA, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(FLT_ZVS_HBA, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(FLT_ZVS_HBA, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(FLT_ZVS_HBA, GPIO_CORE_CPU1);
}
void FLT_ZVS_HBB_init(){
	GPIO_setPadConfig(FLT_ZVS_HBB, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(FLT_ZVS_HBB, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(FLT_ZVS_HBB, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(FLT_ZVS_HBB, GPIO_CORE_CPU1);
}
void IN_DIO1_init(){
	GPIO_setPadConfig(IN_DIO1, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO1, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO1, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO1, GPIO_CORE_CPU1);
}
void IN_DIO2_init(){
	GPIO_setPadConfig(IN_DIO2, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO2, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO2, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO2, GPIO_CORE_CPU1);
}
void IN_DIO3_init(){
	GPIO_writePin(IN_DIO3, 0);
	GPIO_setPadConfig(IN_DIO3, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO3, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO3, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO3, GPIO_CORE_CPU1);
}
void IN_DIO4_init(){
	GPIO_setPadConfig(IN_DIO4, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO4, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO4, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO4, GPIO_CORE_CPU1);
}
void IN_DIO5_init(){
	GPIO_setPadConfig(IN_DIO5, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO5, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO5, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO5, GPIO_CORE_CPU1);
}

//*****************************************************************************
//
// INTERRUPT Configurations
//
//*****************************************************************************
void INTERRUPT_init(){
	
	// Interrupt Setings for INT_ADC_A_1
	Interrupt_register(INT_ADC_A_1, &INT_ADC_ZVS_ISR);
	Interrupt_enable(INT_ADC_A_1);
}
//*****************************************************************************
//
// SPI Configurations
//
//*****************************************************************************
void SPI_init(){
	SPI_MCU2_init();
	SPI_FPGA_init();
}

void SPI_MCU2_init(){
	SPI_disableModule(SPI_MCU2_BASE);
	SPI_setConfig(SPI_MCU2_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
				  SPI_MODE_CONTROLLER, 5000000, 16);
	SPI_setPTESignalPolarity(SPI_MCU2_BASE, SPI_PTE_ACTIVE_LOW);
	SPI_enableFIFO(SPI_MCU2_BASE);
	SPI_setFIFOInterruptLevel(SPI_MCU2_BASE, SPI_FIFO_TX8, SPI_FIFO_RX8);
	SPI_clearInterruptStatus(SPI_MCU2_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_enableInterrupt(SPI_MCU2_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_disableLoopback(SPI_MCU2_BASE);
	SPI_setEmulationMode(SPI_MCU2_BASE, SPI_EMULATION_STOP_AFTER_TRANSMIT);
	SPI_enableModule(SPI_MCU2_BASE);
}
void SPI_FPGA_init(){
	SPI_disableModule(SPI_FPGA_BASE);
	SPI_setConfig(SPI_FPGA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
				  SPI_MODE_CONTROLLER, 1000000, 16);
	SPI_setPTESignalPolarity(SPI_FPGA_BASE, SPI_PTE_ACTIVE_LOW);
	SPI_enableFIFO(SPI_FPGA_BASE);
	SPI_setFIFOInterruptLevel(SPI_FPGA_BASE, SPI_FIFO_TX10, SPI_FIFO_RX10);
	SPI_clearInterruptStatus(SPI_FPGA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_enableInterrupt(SPI_FPGA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_disableLoopback(SPI_FPGA_BASE);
	SPI_setEmulationMode(SPI_FPGA_BASE, SPI_EMULATION_FREE_RUN);
	SPI_enableModule(SPI_FPGA_BASE);
}

//*****************************************************************************
//
// SYNC Scheme Configurations
//
//*****************************************************************************
void SYNC_init(){
	SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT);
	//
	// SOCA
	//
	SysCtl_enableExtADCSOCSource(0);
	//
	// SOCB
	//
	SysCtl_enableExtADCSOCSource(0);
}

and I set "SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL11_ADC, 2, SYSCTL_CPUSEL_CPU2);" the ADCB1 interrupt cannot be get in CPU2.

When I register the interrupt with SysConfig in CPU1:

this is the board.c code:

/*
 * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include "board.h"

//*****************************************************************************
//
// Board Configurations
// Initializes the rest of the modules. 
// Call this function in your application if you wish to do all module 
// initialization.
// If you wish to not use some of the initializations, instead of the 
// Board_init use the individual Module_inits
//
//*****************************************************************************
void Board_init()
{
	EALLOW;

	PinMux_init();
	SYNC_init();
	ADC_init();
	DMA_init();
	EPWM_init();
	GPIO_init();
	SPI_init();
	INTERRUPT_init();

	EDIS;
}

//*****************************************************************************
//
// PINMUX Configurations
//
//*****************************************************************************
void PinMux_init()
{
	//
	// PinMux for modules assigned to CPU1
	//
	
	//
	// EPWM1 -> HB_A Pinmux
	//
	GPIO_setPinConfig(HB_A_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(HB_A_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_A_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(HB_A_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(HB_A_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_A_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM2 -> HB_B Pinmux
	//
	GPIO_setPinConfig(HB_B_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(HB_B_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_B_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(HB_B_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(HB_B_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(HB_B_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM6 -> VR_A Pinmux
	//
	GPIO_setPinConfig(VR_A_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(VR_A_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_A_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(VR_A_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(VR_A_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_A_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM7 -> VR_B Pinmux
	//
	GPIO_setPinConfig(VR_B_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(VR_B_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_B_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(VR_B_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(VR_B_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_B_EPWMB_GPIO, GPIO_QUAL_SYNC);

	//
	// EPWM8 -> VR_C Pinmux
	//
	GPIO_setPinConfig(VR_C_EPWMA_PIN_CONFIG);
	GPIO_setPadConfig(VR_C_EPWMA_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_C_EPWMA_GPIO, GPIO_QUAL_SYNC);

	GPIO_setPinConfig(VR_C_EPWMB_PIN_CONFIG);
	GPIO_setPadConfig(VR_C_EPWMB_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(VR_C_EPWMB_GPIO, GPIO_QUAL_SYNC);

	// GPIO31 -> LED1_MCU1_GPIO Pinmux
	GPIO_setPinConfig(GPIO_31_GPIO31);
	// GPIO34 -> LED2_MCU1_GPIO Pinmux
	GPIO_setPinConfig(GPIO_34_GPIO34);
	// GPIO67 -> DI6_ME Pinmux
	GPIO_setPinConfig(GPIO_67_GPIO67);
	// GPIO36 -> DIO4 Pinmux
	GPIO_setPinConfig(GPIO_36_GPIO36);
	// GPIO37 -> DIO5 Pinmux
	GPIO_setPinConfig(GPIO_37_GPIO37);
	// GPIO38 -> DIO6 Pinmux
	GPIO_setPinConfig(GPIO_38_GPIO38);
	// GPIO39 -> DIO7 Pinmux
	GPIO_setPinConfig(GPIO_39_GPIO39);
	// GPIO40 -> DIO8 Pinmux
	GPIO_setPinConfig(GPIO_40_GPIO40);
	// GPIO41 -> DIO9 Pinmux
	GPIO_setPinConfig(GPIO_41_GPIO41);
	// GPIO49 -> FLT_ZVS_HBA Pinmux
	GPIO_setPinConfig(GPIO_49_GPIO49);
	// GPIO50 -> FLT_ZVS_HBB Pinmux
	GPIO_setPinConfig(GPIO_50_GPIO50);
	// GPIO55 -> IN_DIO1 Pinmux
	GPIO_setPinConfig(GPIO_55_GPIO55);
	// GPIO56 -> IN_DIO2 Pinmux
	GPIO_setPinConfig(GPIO_56_GPIO56);
	// GPIO57 -> IN_DIO3 Pinmux
	GPIO_setPinConfig(GPIO_57_GPIO57);
	// GPIO58 -> IN_DIO4 Pinmux
	GPIO_setPinConfig(GPIO_58_GPIO58);
	// GPIO59 -> IN_DIO5 Pinmux
	GPIO_setPinConfig(GPIO_59_GPIO59);
	//
	// SPIB -> SPI_MCU2 Pinmux
	//
	GPIO_setPinConfig(SPI_MCU2_SPIPICO_PIN_CONFIG);
	GPIO_setPadConfig(SPI_MCU2_SPIPICO_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_MCU2_SPIPICO_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_MCU2_SPIPOCI_PIN_CONFIG);
	GPIO_setPadConfig(SPI_MCU2_SPIPOCI_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_MCU2_SPIPOCI_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_MCU2_SPICLK_PIN_CONFIG);
	GPIO_setPadConfig(SPI_MCU2_SPICLK_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_MCU2_SPICLK_GPIO, GPIO_QUAL_ASYNC);

	//
	// SPID -> SPI_FPGA Pinmux
	//
	GPIO_setPinConfig(SPI_FPGA_SPIPICO_PIN_CONFIG);
	GPIO_setPadConfig(SPI_FPGA_SPIPICO_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_FPGA_SPIPICO_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_FPGA_SPIPOCI_PIN_CONFIG);
	GPIO_setPadConfig(SPI_FPGA_SPIPOCI_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_FPGA_SPIPOCI_GPIO, GPIO_QUAL_ASYNC);

	GPIO_setPinConfig(SPI_FPGA_SPICLK_PIN_CONFIG);
	GPIO_setPadConfig(SPI_FPGA_SPICLK_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(SPI_FPGA_SPICLK_GPIO, GPIO_QUAL_ASYNC);


}

//*****************************************************************************
//
// ADC Configurations
//
//*****************************************************************************
void ADC_init(){
	ADC_B_init();
	ADC_A_init();
}

void ADC_B_init(){
	//
	// ADC Initialization: Write ADC configurations and power up the ADC
	//
	// Configures the analog-to-digital converter module prescaler.
	//
	ADC_setPrescaler(ADC_B_BASE, ADC_CLK_DIV_4_0);
	//
	// Configures the analog-to-digital converter resolution and signal mode.
	//
	ADC_setMode(ADC_B_BASE, ADC_RESOLUTION_12BIT, ADC_MODE_SINGLE_ENDED);
	//
	// Sets the timing of the end-of-conversion pulse
	//
	ADC_setInterruptPulseMode(ADC_B_BASE, ADC_PULSE_END_OF_CONV);
	//
	// Powers up the analog-to-digital converter core.
	//
	ADC_enableConverter(ADC_B_BASE);
	//
	// Delay for 1ms to allow ADC time to power up
	//
	DEVICE_DELAY_US(500);
	//
	// SOC Configuration: Setup ADC EPWM channel and trigger settings
	//
	// Disables SOC burst mode.
	//
	ADC_disableBurstMode(ADC_B_BASE);
	//
	// Sets the priority mode of the SOCs.
	//
	ADC_setSOCPriority(ADC_B_BASE, ADC_PRI_ALL_ROUND_ROBIN);
	//
	// Start of Conversion 0 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 0
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN0
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_B_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN0, 15U);
	ADC_setInterruptSOCTrigger(ADC_B_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 1 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 1
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_B_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(ADC_B_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 2 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 2
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN2
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_B_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN2, 15U);
	ADC_setInterruptSOCTrigger(ADC_B_BASE, ADC_SOC_NUMBER2, ADC_INT_SOC_TRIGGER_NONE);
	//
	// ADC Interrupt 1 Configuration
	// 		Source	: ADC_SOC_NUMBER0
	// 		Interrupt Source: enabled
	// 		Continuous Mode	: disabled
	//
	//
	ADC_setInterruptSource(ADC_B_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER0);
	ADC_clearInterruptStatus(ADC_B_BASE, ADC_INT_NUMBER1);
	ADC_disableContinuousMode(ADC_B_BASE, ADC_INT_NUMBER1);
	ADC_enableInterrupt(ADC_B_BASE, ADC_INT_NUMBER1);
}
void ADC_A_init(){
	//
	// ADC Initialization: Write ADC configurations and power up the ADC
	//
	// Configures the analog-to-digital converter module prescaler.
	//
	ADC_setPrescaler(ADC_A_BASE, ADC_CLK_DIV_4_0);
	//
	// Configures the analog-to-digital converter resolution and signal mode.
	//
	ADC_setMode(ADC_A_BASE, ADC_RESOLUTION_12BIT, ADC_MODE_SINGLE_ENDED);
	//
	// Sets the timing of the end-of-conversion pulse
	//
	ADC_setInterruptPulseMode(ADC_A_BASE, ADC_PULSE_END_OF_CONV);
	//
	// Powers up the analog-to-digital converter core.
	//
	ADC_enableConverter(ADC_A_BASE);
	//
	// Delay for 1ms to allow ADC time to power up
	//
	DEVICE_DELAY_US(500);
	//
	// SOC Configuration: Setup ADC EPWM channel and trigger settings
	//
	// Disables SOC burst mode.
	//
	ADC_disableBurstMode(ADC_A_BASE);
	//
	// Sets the priority mode of the SOCs.
	//
	ADC_setSOCPriority(ADC_A_BASE, ADC_PRI_ALL_ROUND_ROBIN);
	//
	// Start of Conversion 0 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 0
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN14
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN14, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 1 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 1
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN15
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER1, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN15, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER1, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 2 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 2
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN1
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER2, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN1, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER2, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 3 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 3
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN2
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER3, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN2, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER3, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 4 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 4
	//	  	Trigger			: ADC_TRIGGER_EPWM8_SOCA
	//	  	Channel			: ADC_CH_ADCIN3
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER4, ADC_TRIGGER_EPWM8_SOCA, ADC_CH_ADCIN3, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER4, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 5 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 5
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 20 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER5, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 20U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER5, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 6 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 6
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN5
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER6, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN5, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER6, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 8 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 8
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER8, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER8, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 9 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 9
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER9, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER9, ADC_INT_SOC_TRIGGER_NONE);
	//
	// Start of Conversion 10 Configuration
	//
	//
	// Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger.
	// 	  	SOC number		: 10
	//	  	Trigger			: ADC_TRIGGER_EPWM6_SOCA
	//	  	Channel			: ADC_CH_ADCIN4
	//	 	Sample Window	: 15 SYSCLK cycles
	//		Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE
	//
	ADC_setupSOC(ADC_A_BASE, ADC_SOC_NUMBER10, ADC_TRIGGER_EPWM6_SOCA, ADC_CH_ADCIN4, 15U);
	ADC_setInterruptSOCTrigger(ADC_A_BASE, ADC_SOC_NUMBER10, ADC_INT_SOC_TRIGGER_NONE);
	//
	// ADC Interrupt 1 Configuration
	// 		Source	: ADC_SOC_NUMBER5
	// 		Interrupt Source: enabled
	// 		Continuous Mode	: disabled
	//
	//
	ADC_setInterruptSource(ADC_A_BASE, ADC_INT_NUMBER1, ADC_SOC_NUMBER5);
	ADC_clearInterruptStatus(ADC_A_BASE, ADC_INT_NUMBER1);
	ADC_disableContinuousMode(ADC_A_BASE, ADC_INT_NUMBER1);
	ADC_enableInterrupt(ADC_A_BASE, ADC_INT_NUMBER1);
}


//*****************************************************************************
//
// DMA Configurations
//
//*****************************************************************************
void DMA_init(){
    DMA_initController();
	SPI_MCU2_TX_DMA_init();
	SPI_MCU2_RX_DMA_init();
	SPI_FPGA_RX_DMA_init();
	SPI_FPGA_TX_DMA_init();
}

void SPI_MCU2_TX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_STOP);
    DMA_configAddresses(SPI_MCU2_TX_DMA_BASE, SPI_MCU2_TX_DMA_ADDRESS, dma1TxAddr);
    DMA_configBurst(SPI_MCU2_TX_DMA_BASE, 8U, 1, 0);
    DMA_configTransfer(SPI_MCU2_TX_DMA_BASE, 8U, 1, 0);
    DMA_configWrap(SPI_MCU2_TX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_MCU2_TX_DMA_BASE, SPI_MCU2_TX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_MCU2_TX_DMA_BASE);
    DMA_stopChannel(SPI_MCU2_TX_DMA_BASE);
}
void SPI_MCU2_RX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_STOP);
    DMA_configAddresses(SPI_MCU2_RX_DMA_BASE, dma2RxAddr, SPI_MCU2_RX_DMA_ADDRESS);
    DMA_configBurst(SPI_MCU2_RX_DMA_BASE, 8U, 0, 1);
    DMA_configTransfer(SPI_MCU2_RX_DMA_BASE, 8U, 0, 1);
    DMA_configWrap(SPI_MCU2_RX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_MCU2_RX_DMA_BASE, SPI_MCU2_RX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_MCU2_RX_DMA_BASE);
    DMA_stopChannel(SPI_MCU2_RX_DMA_BASE);
}
void SPI_FPGA_RX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_FREE_RUN);
    DMA_configAddresses(SPI_FPGA_RX_DMA_BASE, dma4RxAddr, SPI_FPGA_RX_DMA_ADDRESS);
    DMA_configBurst(SPI_FPGA_RX_DMA_BASE, 10U, 0, 1);
    DMA_configTransfer(SPI_FPGA_RX_DMA_BASE, 5U, 0, 1);
    DMA_configWrap(SPI_FPGA_RX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_FPGA_RX_DMA_BASE, SPI_FPGA_RX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_FPGA_RX_DMA_BASE);
    DMA_stopChannel(SPI_FPGA_RX_DMA_BASE);
}
void SPI_FPGA_TX_DMA_init(){
    DMA_setEmulationMode(DMA_EMULATION_STOP);
    DMA_configAddresses(SPI_FPGA_TX_DMA_BASE, SPI_FPGA_TX_DMA_ADDRESS, dma3TxAddr);
    DMA_configBurst(SPI_FPGA_TX_DMA_BASE, 5U, 1, 0);
    DMA_configTransfer(SPI_FPGA_TX_DMA_BASE, 10U, 1, 0);
    DMA_configWrap(SPI_FPGA_TX_DMA_BASE, 65535U, 0, 65535U, 0);
    DMA_configMode(SPI_FPGA_TX_DMA_BASE, SPI_FPGA_TX_DMA_TRIGGER, DMA_CFG_ONESHOT_DISABLE | DMA_CFG_CONTINUOUS_ENABLE | DMA_CFG_SIZE_16BIT);
    DMA_enableTrigger(SPI_FPGA_TX_DMA_BASE);
    DMA_stopChannel(SPI_FPGA_TX_DMA_BASE);
}

//*****************************************************************************
//
// EPWM Configurations
//
//*****************************************************************************
void EPWM_init(){
    EPWM_enableGlobalLoad(HB_A_BASE);	
    EPWM_setGlobalLoadEventPrescale(HB_A_BASE, 1);	
    EPWM_setEmulationMode(HB_A_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(HB_A_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(HB_A_BASE, 999);	
    EPWM_setTimeBaseCounter(HB_A_BASE, 0);	
    EPWM_setTimeBaseCounterMode(HB_A_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(HB_A_BASE);	
    EPWM_setPhaseShift(HB_A_BASE, 1);	
    EPWM_enableSyncOutPulseSource(HB_A_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(HB_A_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(HB_A_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_A_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(HB_A_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_A_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(HB_A_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(HB_A_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(HB_A_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(HB_A_BASE, 10);	
    EPWM_setDeadBandDelayMode(HB_A_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(HB_A_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(HB_A_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(HB_A_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(HB_A_BASE);	
    EPWM_enableADCTrigger(HB_A_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(HB_A_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(HB_A_BASE, EPWM_SOC_A, 1);	
    EPWM_enableGlobalLoad(HB_B_BASE);	
    EPWM_setGlobalLoadEventPrescale(HB_B_BASE, 1);	
    EPWM_setEmulationMode(HB_B_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(HB_B_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(HB_B_BASE, 999);	
    EPWM_setupEPWMLinks(HB_B_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(HB_B_BASE, 0);	
    EPWM_setTimeBaseCounterMode(HB_B_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(HB_B_BASE);	
    EPWM_setPhaseShift(HB_B_BASE, 1);	
    EPWM_enableSyncOutPulseSource(HB_B_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(HB_B_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(HB_B_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_B_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(HB_B_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(HB_B_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(HB_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(HB_B_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(HB_B_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(HB_B_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(HB_B_BASE, 10);	
    EPWM_setDeadBandDelayMode(HB_B_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(HB_B_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(HB_B_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(HB_B_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(HB_B_BASE);	
    EPWM_enableGlobalLoad(VR_A_BASE);	
    EPWM_setGlobalLoadEventPrescale(VR_A_BASE, 1);	
    EPWM_setEmulationMode(VR_A_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(VR_A_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(VR_A_BASE, 999);	
    EPWM_setupEPWMLinks(VR_A_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(VR_A_BASE, 0);	
    EPWM_setTimeBaseCounterMode(VR_A_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(VR_A_BASE);	
    EPWM_setPhaseShift(VR_A_BASE, 1);	
    EPWM_enableSyncOutPulseSource(VR_A_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(VR_A_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(VR_A_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_A_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(VR_A_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_A_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_A_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(VR_A_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(VR_A_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(VR_A_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(VR_A_BASE, 10);	
    EPWM_setDeadBandDelayMode(VR_A_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(VR_A_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(VR_A_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(VR_A_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(VR_A_BASE);	
    EPWM_enableADCTrigger(VR_A_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(VR_A_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(VR_A_BASE, EPWM_SOC_A, 1);	
    EPWM_enableGlobalLoad(VR_B_BASE);	
    EPWM_setGlobalLoadEventPrescale(VR_B_BASE, 1);	
    EPWM_setEmulationMode(VR_B_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(VR_B_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(VR_B_BASE, 999);	
    EPWM_setupEPWMLinks(VR_B_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(VR_B_BASE, 0);	
    EPWM_setTimeBaseCounterMode(VR_B_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(VR_B_BASE);	
    EPWM_setPhaseShift(VR_B_BASE, 1);	
    EPWM_enableSyncOutPulseSource(VR_B_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(VR_B_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(VR_B_BASE, EPWM_COUNTER_COMPARE_A, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_B_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(VR_B_BASE, EPWM_COUNTER_COMPARE_B, 0);	
    EPWM_setCounterCompareShadowLoadMode(VR_B_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_B_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(VR_B_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(VR_B_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(VR_B_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(VR_B_BASE, 10);	
    EPWM_setDeadBandDelayMode(VR_B_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(VR_B_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(VR_B_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(VR_B_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(VR_B_BASE);	
    EPWM_enableGlobalLoad(VR_C_BASE);	
    EPWM_setGlobalLoadEventPrescale(VR_C_BASE, 1);	
    EPWM_setEmulationMode(VR_C_BASE, EPWM_EMULATION_FREE_RUN);	
    EPWM_setClockPrescaler(VR_C_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);	
    EPWM_setTimeBasePeriod(VR_C_BASE, 999);	
    EPWM_setupEPWMLinks(VR_C_BASE, EPWM_LINK_WITH_EPWM_6, EPWM_LINK_TBPRD);	
    EPWM_setTimeBaseCounter(VR_C_BASE, 0);	
    EPWM_setTimeBaseCounterMode(VR_C_BASE, EPWM_COUNTER_MODE_UP);	
    EPWM_enablePhaseShiftLoad(VR_C_BASE);	
    EPWM_setPhaseShift(VR_C_BASE, 1);	
    EPWM_enableSyncOutPulseSource(VR_C_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);	
    EPWM_setSyncPulseSource(VR_C_BASE, HRPWM_PWMSYNC_SOURCE_ZERO);	
    EPWM_setCounterCompareValue(VR_C_BASE, EPWM_COUNTER_COMPARE_A, 400);	
    EPWM_setCounterCompareShadowLoadMode(VR_C_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setCounterCompareValue(VR_C_BASE, EPWM_COUNTER_COMPARE_B, 600);	
    EPWM_setCounterCompareShadowLoadMode(VR_C_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);	
    EPWM_setActionQualifierAction(VR_C_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);	
    EPWM_setDeadBandDelayPolarity(VR_C_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);	
    EPWM_setDeadBandDelayMode(VR_C_BASE, EPWM_DB_RED, true);	
    EPWM_setRisingEdgeDelayCountShadowLoadMode(VR_C_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO);	
    EPWM_setRisingEdgeDelayCount(VR_C_BASE, 10);	
    EPWM_setDeadBandDelayMode(VR_C_BASE, EPWM_DB_FED, true);	
    EPWM_setFallingEdgeDelayCountShadowLoadMode(VR_C_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);	
    EPWM_setFallingEdgeDelayCount(VR_C_BASE, 10);	
    EPWM_disableRisingEdgeDelayCountShadowLoadMode(VR_C_BASE);	
    EPWM_disableFallingEdgeDelayCountShadowLoadMode(VR_C_BASE);	
    EPWM_enableADCTrigger(VR_C_BASE, EPWM_SOC_A);	
    EPWM_setADCTriggerSource(VR_C_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO);	
    EPWM_setADCTriggerEventPrescale(VR_C_BASE, EPWM_SOC_A, 1);	
}

//*****************************************************************************
//
// GPIO Configurations
//
//*****************************************************************************
void GPIO_init(){
	LED1_MCU1_GPIO_init();
	LED2_MCU1_GPIO_init();
	DI6_ME_init();
	DIO4_init();
	DIO5_init();
	DIO6_init();
	DIO7_init();
	DIO8_init();
	DIO9_init();
	FLT_ZVS_HBA_init();
	FLT_ZVS_HBB_init();
	IN_DIO1_init();
	IN_DIO2_init();
	IN_DIO3_init();
	IN_DIO4_init();
	IN_DIO5_init();
}

void LED1_MCU1_GPIO_init(){
	GPIO_writePin(LED1_MCU1_GPIO, 1);
	GPIO_setPadConfig(LED1_MCU1_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(LED1_MCU1_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(LED1_MCU1_GPIO, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(LED1_MCU1_GPIO, GPIO_CORE_CPU1);
}
void LED2_MCU1_GPIO_init(){
	GPIO_writePin(LED2_MCU1_GPIO, 1);
	GPIO_setPadConfig(LED2_MCU1_GPIO, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(LED2_MCU1_GPIO, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(LED2_MCU1_GPIO, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(LED2_MCU1_GPIO, GPIO_CORE_CPU2);
}
void DI6_ME_init(){
	GPIO_setPadConfig(DI6_ME, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DI6_ME, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DI6_ME, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(DI6_ME, GPIO_CORE_CPU1);
}
void DIO4_init(){
	GPIO_writePin(DIO4, 0);
	GPIO_setPadConfig(DIO4, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO4, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO4, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO4, GPIO_CORE_CPU1);
}
void DIO5_init(){
	GPIO_writePin(DIO5, 0);
	GPIO_setPadConfig(DIO5, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO5, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO5, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO5, GPIO_CORE_CPU1);
}
void DIO6_init(){
	GPIO_writePin(DIO6, 0);
	GPIO_setPadConfig(DIO6, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO6, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO6, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO6, GPIO_CORE_CPU2);
}
void DIO7_init(){
	GPIO_writePin(DIO7, 0);
	GPIO_setPadConfig(DIO7, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO7, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO7, GPIO_DIR_MODE_OUT);
	GPIO_setControllerCore(DIO7, GPIO_CORE_CPU2);
}
void DIO8_init(){
	GPIO_setPadConfig(DIO8, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO8, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO8, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(DIO8, GPIO_CORE_CPU1);
}
void DIO9_init(){
	GPIO_setPadConfig(DIO9, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(DIO9, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(DIO9, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(DIO9, GPIO_CORE_CPU1);
}
void FLT_ZVS_HBA_init(){
	GPIO_setPadConfig(FLT_ZVS_HBA, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(FLT_ZVS_HBA, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(FLT_ZVS_HBA, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(FLT_ZVS_HBA, GPIO_CORE_CPU1);
}
void FLT_ZVS_HBB_init(){
	GPIO_setPadConfig(FLT_ZVS_HBB, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(FLT_ZVS_HBB, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(FLT_ZVS_HBB, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(FLT_ZVS_HBB, GPIO_CORE_CPU1);
}
void IN_DIO1_init(){
	GPIO_setPadConfig(IN_DIO1, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO1, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO1, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO1, GPIO_CORE_CPU1);
}
void IN_DIO2_init(){
	GPIO_setPadConfig(IN_DIO2, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO2, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO2, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO2, GPIO_CORE_CPU1);
}
void IN_DIO3_init(){
	GPIO_writePin(IN_DIO3, 0);
	GPIO_setPadConfig(IN_DIO3, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO3, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO3, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO3, GPIO_CORE_CPU1);
}
void IN_DIO4_init(){
	GPIO_setPadConfig(IN_DIO4, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO4, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO4, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO4, GPIO_CORE_CPU1);
}
void IN_DIO5_init(){
	GPIO_setPadConfig(IN_DIO5, GPIO_PIN_TYPE_STD);
	GPIO_setQualificationMode(IN_DIO5, GPIO_QUAL_SYNC);
	GPIO_setDirectionMode(IN_DIO5, GPIO_DIR_MODE_IN);
	GPIO_setControllerCore(IN_DIO5, GPIO_CORE_CPU1);
}

//*****************************************************************************
//
// INTERRUPT Configurations
//
//*****************************************************************************
void INTERRUPT_init(){
	
	// Interrupt Setings for INT_ADC_B_1
	Interrupt_register(INT_ADC_B_1, &INT_ADC_VR_ISR);
	Interrupt_enable(INT_ADC_B_1);
	
	// Interrupt Setings for INT_ADC_A_1
	Interrupt_register(INT_ADC_A_1, &INT_ADC_ZVS_ISR);
	Interrupt_enable(INT_ADC_A_1);
}
//*****************************************************************************
//
// SPI Configurations
//
//*****************************************************************************
void SPI_init(){
	SPI_MCU2_init();
	SPI_FPGA_init();
}

void SPI_MCU2_init(){
	SPI_disableModule(SPI_MCU2_BASE);
	SPI_setConfig(SPI_MCU2_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
				  SPI_MODE_CONTROLLER, 5000000, 16);
	SPI_setPTESignalPolarity(SPI_MCU2_BASE, SPI_PTE_ACTIVE_LOW);
	SPI_enableFIFO(SPI_MCU2_BASE);
	SPI_setFIFOInterruptLevel(SPI_MCU2_BASE, SPI_FIFO_TX8, SPI_FIFO_RX8);
	SPI_clearInterruptStatus(SPI_MCU2_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_enableInterrupt(SPI_MCU2_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_disableLoopback(SPI_MCU2_BASE);
	SPI_setEmulationMode(SPI_MCU2_BASE, SPI_EMULATION_STOP_AFTER_TRANSMIT);
	SPI_enableModule(SPI_MCU2_BASE);
}
void SPI_FPGA_init(){
	SPI_disableModule(SPI_FPGA_BASE);
	SPI_setConfig(SPI_FPGA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1,
				  SPI_MODE_CONTROLLER, 1000000, 16);
	SPI_setPTESignalPolarity(SPI_FPGA_BASE, SPI_PTE_ACTIVE_LOW);
	SPI_enableFIFO(SPI_FPGA_BASE);
	SPI_setFIFOInterruptLevel(SPI_FPGA_BASE, SPI_FIFO_TX10, SPI_FIFO_RX10);
	SPI_clearInterruptStatus(SPI_FPGA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_enableInterrupt(SPI_FPGA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
	SPI_disableLoopback(SPI_FPGA_BASE);
	SPI_setEmulationMode(SPI_FPGA_BASE, SPI_EMULATION_FREE_RUN);
	SPI_enableModule(SPI_FPGA_BASE);
}

//*****************************************************************************
//
// SYNC Scheme Configurations
//
//*****************************************************************************
void SYNC_init(){
	SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT);
	//
	// SOCA
	//
	SysCtl_enableExtADCSOCSource(0);
	//
	// SOCB
	//
	SysCtl_enableExtADCSOCSource(0);
}

and I can get the interrupt in both cores, CPU1 and CPU2, but I need to avoid to manage it in CPU1.

Thanks again and regards,

Fabio

0 Ibukun Olumuyiwa over 1 year ago in reply to Fabio Rastrello

TI__Genius 11011 points

Hello Fabio,

This is still a mystery. I can try to debug your code on my end if you send it to me privately. I am curious to get to the root of this.

The other thing I can think of to try is this: I believe when you assigned ownership to CPU2, it didn't work because the ADC was still being configured by CPU1. Can you try assigning ownership to CPU2, and then configure the ADC entirely using CPU2 (you can just copy the portions of the board.c code that apply to ADCB and run them in your CPU2 main function)? Once a peripheral is assigned to CPU2, the registers are no longer readable or writable by CPU1 so it is best to handle the peripheral entirely in CPU2.

Best regards,
Ibukun

0 Fabio Rastrello over 1 year ago in reply to Ibukun Olumuyiwa

Prodigy 120 points

Hi Ibukun,

thanks I will try as you suggested, but I am in integration tests of my code , so I will try in some days... I will let you know.

Thanks again and best regards,

Fabio

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28388D: CPU2 cannot detect ADC interrupt