TMS320F28035: TMS320F28035

Kindly find the picture of command file, please. 

Hello Ozino,

Thanks for responding. Got some clarity in updating the drivers. I will install the latest version of C2000 ware, and wil try the same.

Between, I am using the latest CCS 12.6 Version, and one of the warning with IQ math is rectified now.  

Will keep you posted in the thread after trying the code in latest version. 

Many thanks. 

Prasanth Ram

Hello Prasanth,

Sounds good. Please let us know if you have any additional questions.

Regards,

Ozino

Dear Ozino,

After trying and updating the C2000 ware, I tried my code with the timer example file. Although, I am being succesful with the errorless code, I have problems in  debugging the code. Somewhere, the code is getting loopep during boot. Howver, I still didint get the problem that where I am going wrong. I also checked with mutlple discussions in the TiE forum, but then, I wasnt able able to figure this out. For your kind reference, I have given my code below, can you kindly chck them once please? 

The screen shot of error during Debug id attched in the picture. your kind suggestions will definitely help me to resolve the problem. Thank you in advance  

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include <math.h>
#include <IQmathLib.h>
#include "Solar_F.h"

void Adc_Config(void);
void EPwm1(void);
void EPwm2(void);
void EPwm3(void);
void gpiosetup (void);


CNTL_PI_F cntl_pi1;


Uint16 LoopCount;
Uint16 ConversionCount;
Uint16 Vin_PV[10];
Uint16 Vo_PV[10];
Uint16 Iin_PV[10];
Uint16 Io_PV[10];
float duty1=0.4;
float duty2=0.4;
float duty3=0.5;
float Vin_act,Vo_act, Iin_act,Io_act;
float Gv = 155.0;
float Gi = 2.5;

Uint16 i;

int16 period = 600;
int16 phase = 300;
float PI1_out ;
float reference = 10.0;
float feedback = 5.0;



__interrupt void cpu_timer0_isr(void);
__interrupt void cpu_timer1_isr(void);

void main(void)
{
    // InitFlash();
    //
    // Step 1. Initialize System Control:

    InitSysCtrl();

    EALLOW;                              //interrupts for timer 0
         SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
         EDIS;

         EALLOW;                             //interrupts for timer 1
         SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
         EDIS;
    DINT;

    InitPieCtrl();

    //
    // Disable CPU interrupts and clear all CPU interrupt flags
    //
    IER = 0x0000;
    IFR = 0x0000;


    InitPieVectTable();


    //
    EALLOW;             // This is needed to write to EALLOW protected register
    PieVectTable.TINT0 = &cpu_timer0_isr;
    PieVectTable.TINT1 = &cpu_timer1_isr;
//    PieVectTable.ADCINT1 = &adc_isr;
    EDIS;    // This is needed to disable write to EALLOW protected registers


    InitAdc();  // For this example, init the ADC
    InitCpuTimers();

    ConfigCpuTimer(&CpuTimer0, 60, 100);
    ConfigCpuTimer(&CpuTimer1, 60, 10);
//  CpuTimer0Regs.TCR.bit.TSS = 0;
     CpuTimer0Regs.TCR.all = 0x4000;
     CpuTimer1Regs.TCR.all = 0x4000;
     IER |= M_INT1;
     IER |= M_INT13;
     PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
     PieCtrlRegs.PIEIER1.bit.INTx6 =1;

  gpiosetup ();
  EPwm1();
  EPwm2();
  EPwm3();


 // PI controller solar lib defaults

    CNTL_PI_F_init(&cntl_pi1);
    cntl_pi1.Ki = (0.1);
    cntl_pi1.Kp = (0.2);
    cntl_pi1.Umax = (0.5);
    cntl_pi1.Umin = (0.025);
    cntl_pi1.up = (0.6);
    cntl_pi1.ui = (0.6);



    EINT;                               // Enable Global interrupt INTM
    ERTM;                               // Enable Global realtime interrupt DBGM

    LoopCount = 0;
    ConversionCount = 0;

    // Configure ADC

    EALLOW;
    AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
    AdcRegs.INTSEL1N2.bit.INT1E     = 1; // Enabled ADCINT1
    AdcRegs.INTSEL1N2.bit.INT1CONT  = 0; // Disable ADCINT1 Continuous mode
    AdcRegs.INTSEL1N2.bit.INT1SEL   = 2;  // setup EOC2 to trigger

    // set SOC0 channel select to ADCINA0 and SOC 1 -A1, SOC 2 -A2, SOC 3 -A3, SOC 4 -A4

    AdcRegs.ADCSOC0CTL.bit.CHSEL    = 0;
    AdcRegs.ADCSOC1CTL.bit.CHSEL    = 1;  //set SOC1 channel select to ADCINA1
    AdcRegs.ADCSOC2CTL.bit.CHSEL    = 2;  //set SOC2 channel select to ADCINA2
    AdcRegs.ADCSOC3CTL.bit.CHSEL    = 3;
    AdcRegs.ADCSOC4CTL.bit.CHSEL    = 4;

    // set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts
    // first then SOC1, SOC1,2, 3 then SOC3

    AdcRegs.ADCSOC0CTL.bit.TRIGSEL  = 5;
    AdcRegs.ADCSOC1CTL.bit.TRIGSEL  = 5;
    AdcRegs.ADCSOC2CTL.bit.TRIGSEL  = 5;
    AdcRegs.ADCSOC3CTL.bit.TRIGSEL  = 5;
    AdcRegs.ADCSOC4CTL.bit.TRIGSEL  = 5;

    // set SOC0.SOC1,2, 3,4 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)

    AdcRegs.ADCSOC0CTL.bit.ACQPS    = 6;
    AdcRegs.ADCSOC1CTL.bit.ACQPS    = 6;
    AdcRegs.ADCSOC2CTL.bit.ACQPS    = 6;
    AdcRegs.ADCSOC3CTL.bit.ACQPS    = 6;
    AdcRegs.ADCSOC4CTL.bit.ACQPS    = 6;
    EDIS;

    for(;;);
//    {
//        LoopCount++;
//    }
}


__interrupt void cpu_timer0_isr(void)
{
    //
    // discard ADCRESULT0 as part of the workaround to the
    // 1st sample errata for rev0
    //
    Vin_PV[ConversionCount] = AdcResult.ADCRESULT0;
    Vo_PV[ConversionCount] = AdcResult.ADCRESULT1;
    Iin_PV[ConversionCount] = AdcResult.ADCRESULT2;
    Io_PV[ConversionCount] = AdcResult.ADCRESULT4;
    Vin_act=(Vin_PV[ConversionCount]*Gv*3.3)/4095;
    Vo_act=(Vo_PV[ConversionCount]*Gv*3.3)/4095;
    Iin_act=(Iin_PV[ConversionCount]*Gi*3.3)/4095;
    Io_act=(Io_PV[ConversionCount]*Gi*3.3)/4095;


// solar lib PI controller command call function

        cntl_pi1.Ref = (1.0);
        cntl_pi1.Fbk = (0.1);
        CNTL_PI_F_FUNC(&cntl_pi1);

//        CNTL_PI_F_MACRO(cntl_pi1);
//        PIstep=cntl_pi1.Out;


    EPwm1Regs.CMPA.half.CMPA = (EPwm1Regs.TBPRD)*duty1;
    EPwm2Regs.CMPA.half.CMPA = (EPwm2Regs.TBPRD)*duty2;


    if(ConversionCount == 9)
    {
        ConversionCount = 0;
    }
    else
    {
        ConversionCount++;
    }
    // Clear ADCINT1 flag reinitialize for next SOC

    if(i==9)
     {
         i=0;
     }
     else
     {
         i++;
     }
//  AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
    CpuTimer0.InterruptCount++;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE

    return;
}

__interrupt void cpu_timer1_isr(void)
{

    EPwm3Regs.CMPA.half.CMPA = (EPwm3Regs.TBPRD)*duty3;
    CpuTimer1.InterruptCount++;
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE

    return;
}

void EPwm1()
{

    EPwm1Regs.ETSEL.bit.SOCAEN  = 1;    // Enable SOC on A group
    EPwm1Regs.ETSEL.bit.SOCASEL = 4;    // Select SOC from from CPMA on upcount
    EPwm1Regs.ETPS.bit.SOCAPRD  = 1;    // Generate pulse on 1st event

    EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
    EPwm1Regs.TBPRD = period/2;                // PWM frequency = 1 / period
    EPwm1Regs.TBPHS.half.TBPHS = 0;
    EPwm1Regs.TBCTR = 0;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream"

            // Counter Compare Submodule Registers
    EPwm1Regs.CMPA.half.CMPA = 0;              // set duty 0% initially
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;

            // Action Qualifier SubModule Registers
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
//
}

void EPwm2()
{

        EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
     //   EPwm2Regs.CMPA.half.CMPA    = 300;       // Set compare A value
        EPwm2Regs.TBPRD            = period/2;   // Set period for ePWM1


        EPwm2Regs.TBPHS.half.TBPHS = 0;           // Phase is 0
        EPwm2Regs.TBCTR = 0;                      // Clear counter

        EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
       // EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
        EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
        EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;


       //code for phase shift start
        EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
        EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

                if ((0 <= phase)&&(phase <= 2))
                {
                    EPwm2Regs.TBPHS.half.TBPHS = (2-phase);
                    EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;    // set to count up after sync
                }
                else if ((2 < phase)&&(phase <= period/2))
                {
                    EPwm2Regs.TBPHS.half.TBPHS = (phase-2);
                    EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;  // set to count down after sync
                }
                else if ((period/2 < phase)&&(phase <= period))
                {
                    EPwm2Regs.TBPHS.half.TBPHS = (period-phase+2);
                    EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;    // set to count up after sync
                }
          EPwm2Regs.CMPA.half.CMPA = 0;
        //code for phase shift end

        EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
     //   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
        EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;

        EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;             // Set PWM1A on CAU
        EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;              // Clear PWM1A on CAD


}

void EPwm3()
{
//
    EPwm3Regs.TBCTL.bit.CLKDIV = 0x000;
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0x001;
    EPwm3Regs.TBCTL.bit.CTRMODE = 2;
    EPwm3Regs.AQCTLA.all = 0x0060;
    EPwm3Regs.AQCTLB.all = 0x0090;
    EPwm3Regs.CMPA.half.CMPA    = 67;       // Set compare A value
    EPwm3Regs.TBPRD            = 125;
    EPwm3Regs.DBFED = 10;
    EPwm3Regs.DBRED = 10;
    EPwm3Regs.DBCTL.bit.OUT_MODE = 3;
    EPwm3Regs.DBCTL.bit.POLSEL = 2;
    EPwm3Regs.DBCTL.bit.IN_MODE = 0;

}
void gpiosetup(void)
{
    EALLOW;

    GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1;    // Disable pull-up on GPIO0 (EPWM1A)
    GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1;    // Disable pull-up on GPIO1 (EPWM1B)
    GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;   // Configure GPIO0 as EPWM1A
    GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;

    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;    // Disable pull-up on GPIO2 (EPWM2A)
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;    // Disable pull-up on GPIO3 (EPWM2B)
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;   // Configure GPIO2 as EPWM2A
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;

    GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1;    // Disable pull-up on GPIO4 (EPWM3A)
    GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1;    // Disable pull-up on GPIO5 (EPWM3B)
    GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1;   // Configure GPIO4 as EPWM3A
    GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1;

    EDIS;
}

Dear Ozino,

Thanks a lot for recommending an alterantive solution. Let me check them and keep it posted here.

Regards,

Prasanth Ram

Dear Ozino,

After extensive try, I found F28035 controller is not compatible (or) limitation to use FPU32 based libraries. Whenever, I try to call a function with folat 32 variables, I am seeing the symbol mising error in the boot loader (even after adding necessary libraries, this happens only in the debug mode) . Kindly correct me if I am wrong please.

Regards,

Prasanth ram

Hi Prasanth,

You're correct that this device does not have built in FPU support on the C28x. Looks like you'll have to leverage the IQmath library. Are you able to migrate to our newer device that has support for FPU?

Regards,

Ozino