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TMS320F280039C: Clarify EPWM ADCSOCAO and ADC triggering

Wayne Huang
Genius 15665 points
Part Number: TMS320F280039C
Other Parts Discussed in Thread: SYSCONFIG

Dear Champs,

I am asking this for our customer.

The user uses EPWM8 counter = 0 to generate EPWMxSOCA to trigger ADC and use GPIO33 to output EPWM8.ADCSOCAO like below.

We are confused the waveforms of ADCSOCAO and need your further clarification.

Like below figure, Channel D2 (in red) is ADCSOCAO and Chaneel D1 (in brown) is EPWM8A.

Questions:

1. The user notices the pulse width of ADCSOCAO may vary a lot sometimes even though the user uses a constant period EPWM8 counter=0 to trigger it. 

Why does it vary sometimes? Does it have any meaning? Does its width have anything to do with ADC sampling time (ACQPS) of the triggered ADC SOC?

2. If we look into below figure in the datasheet, this ADCTRIG should be ADCSOCAO in this case. Is it right?

Is flag ADCSOCFLG.SOCx set (triggered) to high by the "falling edge" of ADCSOCAO and then start sample/hold?

That is, it's the "falling edge" of ADCTRIG/ADCSOCAO rather than the "width" of ADCTRIG/ADCSOCAO that triggers flag ADCSOCFLG.SOCx?

  • 0
    TI__Genius 10951 points

    Hello Wayne,

    The SOCA signal is entirely controlled by the PWM and is not dependent on what happens inside the ADC. If an SOCA signal arrives while another ADC SOC is converting or has a higher priority, then the ADCSOCFLG.SOCx signal for the requested SOC goes high but does not go low until that SOC reaches the top of the priority queue and starts sampling. If another SOCA trigger signal arrives to the same SOC while one is already pending (waiting to start conversion), then the new trigger is discarded, and the SOC overflow flag is set high.

    Regardless, the ADC trigger signal is entirely controlled by the peripheral that sends it (EPWM or CPUTIMER). ADCTRIG is external to the ADC; ADCSOCFLG.SOCx is internal to the ADC. So, if the period of the SOCA signal is irregular, the cause must be with the EPWM.

  • 0 in reply to Ibukun Olumuyiwa
    TI__Genius 15665 points

    Dear Ibukun,

    I understand.

    Would you please confirm if the falling edge rather than the width of ADCTRIG triggers ADCSOCFLG.SOCx?

    If so, the width of ADCTRIG does not matter.

  • 0 in reply to Wayne Huang
    TI__Genius 10951 points

    Hello Wayne,

    The SOC flag goes high on the next cycle after the arrival of the trigger. So, it is the rising edge + 1 cycle. The acquisition window however begins on the falling edge of the SOC flag signal. If there are no pending SOCs, this should be 2 cycles after the arrival of the trigger.

    Best regards,
    Ibukun

  • 0 in reply to Ibukun Olumuyiwa
    TI__Genius 15665 points

    Dear Ibukun,

    From the figure on the top post or the zoom-in figure below in this post, you can see the falling edge of ADCSOCAO is always at EPWM8 counter=0. If the rising edge + 1 of ADCSOCAO is used to trigger SOC flag, it means there is always a delay up to half of EPWM8 period to trigger ADC SOC. Is our understanding correct? If so, it's very strange to have such long delay to trigger ADC.

    Note that EPWM8A is toggled at counter=0.

    That is, we'd like to clarify if ADC SOC is really triggered almost at the point of EPWM counter=0?

    How come EPWM8 counter=0 is falling edge rather than rising edge if ADC SOC flag is triggered by rising edge+1?

  • 0 in reply to Wayne Huang
    TI__Genius 10951 points

    Hello Wayne,

    I have checked with our design team on this; they confirmed to me that the flag gets set 1 cycle after the rising edge of the incoming trigger. Can we double-check the EPWM8 configuration code to see why the ADC SOCA signal comes in the middle of the cycle instead of at the beginning?

    Thanks,
    Ibukun

  • 0 in reply to Ibukun Olumuyiwa
    TI__Genius 15665 points

    Dear Ibukun,

    Please see the code configuration by Sysconfig.

    EPWM8 event setting

    EPWM8 all settings

    ADCSOCAO to GPIO33

    If needed, I can send you the code for review.

  • 0 in reply to Wayne Huang
    TI__Genius 10951 points

    Hello Wayne,

    Please send code for review. Thanks.

    Ibukun

  • 0 in reply to Ibukun Olumuyiwa
    TI__Genius 15665 points

    Dear Ibukun,

    I already sent it to you offline.

  • 0 in reply to Wayne Huang
    TI__Genius 10951 points

    Thanks Wayne. Will revert as soon as I have more.

  • +1 in reply to Ibukun Olumuyiwa
    TI__Genius 10951 points

    Please disregard my previous post.

    I think I have the answer to this:

    1. The ADCSOCA signal coming out of the ePWM is active low, not active high. We'll be filing a ticket to update the TRM to clarify this point.
    2. The ADCSOCAO signal that comes out on the GPIO pin is pulse-stretched. See Figure 20-3 in the TRM, "ePWM Modules and Critical Internal Signal Interconnects."

    This explains the waveform you are seeing on the GPIO33 pin. The code is correctly configured and the SOCA trigger is arriving at the beginning of the period as expected.

    Best regards,
    Ibukun