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Hi Ryan,
A followup question
If we set up an qep interrupt from the cpu:
EQEP_enableInterrupt(M1_QEP_BASE, EQEP_INT_UNIT_TIME_OUT | EQEP_INT_OVERFLOW | EQEP_INT_UNDERFLOW | EQEP_INT_INDEX_EVNT_LATCH); Interrupt_register(M1_QEP_BASE, &M1_eQEP_ISR);
This is my isr
__interrupt void M1_eQEP_ISR(void) { if((EQEP_getInterruptStatus(M1_QEP_BASE) & EQEP_INT_INDEX_EVNT_LATCH) != 0) { //index event has occurred indexEventCountCPU_qep[0]++; EQEP_clearInterruptStatus(M1_QEP_BASE,(EQEP_INT_INDEX_EVNT_LATCH | EQEP_INT_GLOBAL)); } if((EQEP_getInterruptStatus(M1_QEP_BASE) & EQEP_INT_UNIT_TIME_OUT) != 0) { //UTO timeout has occurred ; EQEP_clearInterruptStatus(M1_QEP_BASE,(EQEP_INT_UNIT_TIME_OUT | EQEP_INT_GLOBAL)); } if((EQEP_getInterruptStatus(M1_QEP_BASE) & EQEP_INT_UNDERFLOW) != 0) { //position counter underflow event has occurred pcuEventCountCPU_qep[0]++; EQEP_clearInterruptStatus(M1_QEP_BASE,(EQEP_INT_UNDERFLOW | EQEP_INT_GLOBAL)); } if((EQEP_getInterruptStatus(M1_QEP_BASE) & EQEP_INT_OVERFLOW) != 0) { //position counter overflow event has occurred pcoEventCountCPU_qep[0]++; EQEP_clearInterruptStatus(M1_QEP_BASE,(EQEP_INT_OVERFLOW | EQEP_INT_GLOBAL)); } Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP5); }
And In one of my CLA tasks i already have somthing simillar running:
if (fclVars[0].ptrQEP->QFLG.all & CLA_QEP_FLAG_IEL_EVENT) { indexCountCLA[0]++; fclVars[0].ptrQEP->QCLR.bit.IEL = 1; } if (fclVars[0].ptrQEP->QFLG.all & CLA_QEP_FLAG_PCU_EVENT) { indexCountCLAUnderflowPCU[0]++; //indexCountCLAOverflowPCO[0] = 0; fclVars[0].ptrQEP->QCLR.bit.PCU = 1; } if (fclVars[0].ptrQEP->QFLG.all & CLA_QEP_FLAG_PCO_EVENT) { indexCountCLAOverflowPCO[0]++; //indexCountCLAUnderflowPCU[0] = 0; fclVars[0].ptrQEP->QCLR.bit.PCO = 1; }
Is it possible to run both these simultaniously for comparision? I want to compare the qep performance from cpu and cla at once, ideally there should be no difference but would like to validate this none the less.
Hi Rayn, thanks for the reply, my doubt here is, can we access the same QEP module from the CPU and CLA simultanously?
For example , here what happens if i clear the IEL interrupt from CPU and CLA,which one will take priority?
What are the sources of the interrupts occurring from the CLA and CPU? Are they the same source? Ideally you only have either CPU or CLA assigned to what is generating the interrupt and clearing the interrupt to avoid these simultaneous flag clears.
Best,
Ryan Ma