TMS320F28069: fft on cla on tms320f28069

Hi Sanjay,

Did you use one of the CLA examples in C2000ware as a starting point for your code? If not, I would suggest starting from one of the examples and adding in your FFT calculation. For the TMS320F28069, these can be found in the [C2000ware install]/device_support/f2806x/examples/cla folder.

Best Regards,

Delaney

yes already i followed the same example, please check my code and help me if i missed something

Hi Sanjay,

Linked here is a workshop video that shows how to migrate FFT calculation code over to the CLA. Can you try running the code shown here in a F2806x project? The project files can be downloaded at the bottom of the page. This example uses a F2937D, which has some slight CLA module enhancements from the F2806x, but I don't believe that should be an issue.

Below are some other threads discussing FFT calculation on the CLA for your reference as well.

TMS320F28379D: Purpose of CLA FFT Table - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums

TMS320F28379D: Moving FFT from CPU1 to CLA (bad computation) - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums

Best Regards,

Delaney

I followed these posts and refined my cmd file as descrbed below, but there is a new problem now, i am getting some random values of fft output, please have a look and let me know if I am missing something in this cmd file:(Please note that my code is working fine without CLA, but when I use cla, i am it is providing random values of fft output)

/*
// TI File $Revision: /main/3 $
// Checkin $Date: March 3, 2011 13:45:53 $
//###########################################################################
//
// FILE: F28069.cmd
//
// TITLE: Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: 2806x C/C++ Header Files V1.10 $
// $Release Date: April 7, 2011 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add: F2806x_Headers_BIOS.cmd
// For nonBIOS applications add: F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections

Notes:
Memory blocks on F28069 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.

Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x400
-stack 0x400

// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
//RAML0 : origin = 0x008000, length = 0x000800 /* on-chip RAM block L0 */
//RAML1 : origin = 0x008800, length = 0x000400 /* on-chip RAM block L1 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */

FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */

FPUTABLES : origin = 0x3FD590, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */

ROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */

BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x000350 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
//RAML2 : origin = 0x008C00, length = 0x000400 /* on-chip RAM block L2 */
RAML3 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */
RAML5 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L5 */
RAML6 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L6 */
RAML7 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L7 */
RAML8 : origin = 0x00F000, length = 0x005000 /* on-chip RAM block L8 */
USB_RAM : origin = 0x040000, length = 0x000800 /* USB RAM */
FLASHB : origin = 0x3F0000, length = 0x004000 /* on-chip FLASH */

CLARAM0 : origin = 0x008800, length = 0x000400 /*L1 DSPSARAM*/
CLARAM1 : origin = 0x008C00, length = 0x000400 /*L2 DSPSARAM*/
CLARAM2 : origin = 0x008000, length = 0x000800

CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}

/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/

SECTIONS
{

/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN, PAGE = 0
// ramfuncs : LOAD = FLASHD,
// RUN = RAML0,
// PAGE = 0

ramfuncs : LOAD = FLASHB,
RUN = RAML8,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
LOAD_SIZE(_RamfuncsLoadSize),
PAGE = 1

csmpasswds : > CSM_PWL_P0, PAGE = 0
csm_rsvd : > CSM_RSVD, PAGE = 0

/* Allocate uninitialized data sections: */
.stack : > RAMM1, PAGE = 1
.ebss : > RAML4, PAGE = 1
.esysmem : > RAML6, PAGE = 1
.cio : > RAML5, PAGE = 1

/* Initialized sections to go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA, PAGE = 0
.switch : > FLASHA, PAGE = 0

/* Allocate IQ math areas: */
IQmath : > FLASHA, PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD

/* Allocate FPU math areas: */
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD

IOBuffer : > CLARAM2, PAGE = 1//ALIGN=512,
RFFTdata2 : > CLARAM2, PAGE = 1//ADDED RAML456
RFFTdata3 : > RAML7, PAGE = 1
RFFTdata4 : > RAML8, PAGE = 1 //FPUfftTables

/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{

IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{

IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

}
*/

/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */

Cla1Prog : LOAD = FLASHB,
RUN = RAML3,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 1
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
Cla1DataRam0 : > CLARAM0, PAGE = 1
Cla1DataRam1 : > CLARAM1, PAGE = 1
Cla1DataRam2 : > CLARAM2, PAGE = 1

//CLA1mathTables : > RAML7,
// LOAD_START(_Cla1mathTablesLoadStart),
//LOAD_END(_Cla1mathTablesLoadEnd),
//LOAD_SIZE(_Cla1mathTablesLoadSize),
// RUN_START(_Cla1mathTablesRunStart),
// PAGE = 1

CLA1mathTables : LOAD = FLASHB,
RUN = CLARAM1,
RUN_START(CLA1fftTablesRunStart),
LOAD_START(_Cla1mathTablesLoadStart),
LOAD_END(_Cla1mathTablesLoadEnd),
LOAD_SIZE(_Cla1mathTablesLoadSize),
RUN_START(_Cla1mathTablesRunStart),
PAGE = 1

CLA1fftTables : LOAD = FLASHB,
RUN = RAML4,
RUN_START(CLA1mathTablesRunStart),
LOAD_START(CLA1fftTablesLoadStart),
LOAD_SIZE(CLA1fftTablesLoadSize),
PAGE = 1
// CLA1fftTables : > RAML4,
//LOAD_START(_Cla1fftTablesLoadStart),
//LOAD_END(_Cla1fftTablesLoadEnd),
//LOAD_SIZE(_Cla1fftTablesLoadSize),
//RUN_START(_Cla1fftTablesRunStart),
//PAGE = 1
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > CLARAM0,
PAGE = 1
.bss_cla : > CLARAM0, PAGE = 1
.const_cla : > CLARAM0, PAGE = 1
.scratchpad : > CLARAM0, PAGE = 1

.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS, PAGE = 0, TYPE = DSECT
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Hi Sanjay,

Can you attach your code as files instead of as text? I will look through to see if I can find any issues.

Thanks,

Delaney

/*
// TI File $Revision: /main/3 $
// Checkin $Date: March 3, 2011   13:45:53 $
//###########################################################################
//
// FILE:    F28069.cmd
//
// TITLE:   Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: 2806x C/C++ Header Files V1.10 $
// $Release Date: April 7, 2011 $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the
//   distribution.
//
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/
_Cla1Prog_Start = _Cla1funcsRunStart;
-heap 0x400
-stack 0x400

// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
 CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   //RAML0       : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 */
   //RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x000350     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   //RAML2       : origin = 0x008C00, length = 0x000400     /* on-chip RAM block L2 */
   RAML3       : origin = 0x009000, length = 0x001000	  /* on-chip RAM block L3 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x001000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00D000, length = 0x001000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x00E000, length = 0x001000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x00F000, length = 0x005000     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */

   CLARAM0              : origin = 0x008800, length = 0x000400		/*L1 DSPSARAM*/
   CLARAM1              : origin = 0x008C00, length = 0x000400		/*L2 DSPSARAM*/
   CLARAM2				: origin = 0x008000, length = 0x000800

   CLA1_MSGRAMLOW       : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH      : origin = 0x001500, length = 0x000080
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA,     PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA,     PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
//    ramfuncs         : LOAD = FLASHD,
  //  				   RUN = RAML0,
    //				  PAGE = 0

  ramfuncs            : LOAD = FLASHB,
                       RUN = RAML8,
                     LOAD_START(_RamfuncsLoadStart),
                   LOAD_END(_RamfuncsLoadEnd),
                 RUN_START(_RamfuncsRunStart),
			 LOAD_SIZE(_RamfuncsLoadSize),
           PAGE = 1

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitialized data sections: */
   .stack              : > RAMM1,      PAGE = 1
   .ebss               : > RAML4,      PAGE = 1
   .esysmem            : > RAML6,      PAGE = 1
   .cio                : > RAML5,      PAGE = 1

   /* Initialized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA,     PAGE = 0
   .switch             : > FLASHA,     PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA,     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

   IOBuffer	           : > CLARAM2, ALIGN=4096,   PAGE = 1//ALIGN=512,
   RFFTdata2	           : > CLARAM2,    PAGE = 1//ADDED RAML456
   RFFTdata3	           : > RAML8,      PAGE = 1
   RFFTdata4 	           : > RAML8,      PAGE = 1   //FPUfftTables

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */



  Cla1Prog 			: LOAD = FLASHB,
  					 RUN = RAML3,
                     LOAD_START(_Cla1funcsLoadStart),
                     LOAD_END(_Cla1funcsLoadEnd),
                     LOAD_SIZE(_Cla1funcsLoadSize),
                     RUN_START(_Cla1funcsRunStart),
                     PAGE = 1
   Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
   Cla1DataRam0		: > CLARAM0,		  PAGE = 1
   Cla1DataRam1		: > CLARAM1,		  PAGE = 1
   Cla1DataRam2		: > CLARAM2,		  PAGE = 1

   //CLA1mathTables	: > RAML7,
                     // LOAD_START(_Cla1mathTablesLoadStart),
                      //LOAD_END(_Cla1mathTablesLoadEnd),
                      //LOAD_SIZE(_Cla1mathTablesLoadSize),
                     // RUN_START(_Cla1mathTablesRunStart),
                     // PAGE = 1

    CLA1mathTables	: LOAD = FLASHB,
                      RUN = CLARAM1,
                      RUN_START(CLA1fftTablesRunStart),
                      LOAD_START(_Cla1mathTablesLoadStart),
                      LOAD_END(_Cla1mathTablesLoadEnd),
                      LOAD_SIZE(_Cla1mathTablesLoadSize),
                      RUN_START(_Cla1mathTablesRunStart),
                      PAGE = 1

   CLA1fftTables    :  LOAD = FLASHB,
                       RUN = RAML4,
                       RUN_START(CLA1mathTablesRunStart),
                       LOAD_START(CLA1fftTablesLoadStart),
                       LOAD_SIZE(CLA1fftTablesLoadSize),
                       PAGE = 1
//  CLA1fftTables	: > RAML4,
                      //LOAD_START(_Cla1fftTablesLoadStart),
                      //LOAD_END(_Cla1fftTablesLoadEnd),
                      //LOAD_SIZE(_Cla1fftTablesLoadSize),
                      //RUN_START(_Cla1fftTablesRunStart),
                      //PAGE = 1
  CLAscratch       :
                 { *.obj(CLAscratch)
                 . += CLA_SCRATCHPAD_SIZE;
                 *.obj(CLAscratch_end) } > CLARAM0,
				 PAGE = 1
   .bss_cla		    : > CLARAM0,   PAGE = 1
   .const_cla	    : > CLARAM0,   PAGE = 1
   .scratchpad      : > CLARAM0,   PAGE = 1

   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

#include "Main.h"
#include "stdbool.h"
#include "application.h"

#include "DSP28x_Project.h"     // DSP28x Headerfile
#include "F2806x_Cla_defines.h"
#include "divide_shared.h"
//Externs Functions
//
// Defines
//
#define CLA_PROG_ENABLE      0x0001
#define CLARAM0_ENABLE       0x0010
#define CLARAM1_ENABLE       0x0020
#define CLARAM2_ENABLE       0x0040
#define CLA_RAM0CPUE         0x0100
#define CLA_RAM1CPUE         0x0200
#define CLA_RAM2CPUE         0x0400


//
// CLA ISRs
//
__interrupt void cla1_task1_isr(void);

//
// These are defined by the linker file and used to copy
// the CLA code from its load address to its run address
// in CLA program memory
//
extern Uint16 Cla1funcsLoadStart;
extern Uint16 Cla1funcsLoadEnd;
extern Uint16 Cla1funcsLoadSize;
extern Uint16 Cla1funcsRunStart;
extern Uint16 Cla1Prog_Start;

//
// These are defined by the linker file and used to copy
// the CLA math tables from its load address to its run address
// into one of the CLA data RAMs
//
extern Uint16 Cla1mathTablesLoadStart;
extern Uint16 Cla1mathTablesLoadEnd;
extern Uint16 Cla1mathTablesLoadSize;
extern Uint16 Cla1mathTablesRunStart;


//Globals
Uint16  Sensor_count= 0 ;
extern Uint16 RPM[10];

    //Ram driven Time Dependent Functions
    #pragma CODE_SECTION(DSP28x_usDelay, "ramfuncs");
    #pragma CODE_SECTION(cpu_timer0_isr, "ramfuncs");
    #pragma CODE_SECTION(cpu_timer1_isr, "ramfuncs");
    #pragma CODE_SECTION(ecap2_isr, "ramfuncs");
    #pragma CODE_SECTION(ADXL_Init, "ramfuncs");
    #pragma CODE_SECTION(ADXL_buffer_tick, "ramfuncs");
    #pragma CODE_SECTION(Rpm_Display_Init, "ramfuncs");
    #pragma CODE_SECTION(FPU_FFT_Tick, "ramfuncs");
    #pragma CODE_SECTION(Rpm_Display_Tick, "ramfuncs");
    #pragma CODE_SECTION(scia_msg, "ramfuncs");
    #pragma CODE_SECTION(spi_init, "ramfuncs");
    #pragma CODE_SECTION(spi_fifo_init, "ramfuncs");
    #pragma CODE_SECTION(ADXL359_readRegister, "ramfuncs");
    #pragma CODE_SECTION(ADXL359_writeRegister, "ramfuncs");
    #pragma CODE_SECTION(four_wheeler, "ramfuncs");
// Main
//
void main(void)
{
    // Step 1. Initialize System Control:
       InitSysCtrl();
       InitSciGpio();
       InitECap2Gpio();
       InitSpiaGpio();
       InitECapture();
       InitI2CGpio();
       InitGpio_Button();
       //
       // Disable CPU interrupts and clear all CPU interrupt flags
       DINT;
       //
       InitPieCtrl();


       IER = 0x0000;
       IFR = 0x0000;

       InitPieVectTable();
       //
       // Assign user defined ISR to the PIE vector table
       //
       EALLOW;
       PieVectTable.CLA1_INT1  = &cla1_task1_isr;
       EDIS;
       //
       // Copy over the CLA code(if running in standalone mode from FLASH)
       //
       memcpy(&Cla1funcsRunStart, &Cla1funcsLoadStart,
                (Uint32)&Cla1funcsLoadSize);

       //
       // Copy over the CLA math tables(if running in standalone mode from FLASH
       // and using the CLAMath Library)
       //
       memcpy(&Cla1mathTablesRunStart, &Cla1mathTablesLoadStart,
                (Uint32)&Cla1mathTablesLoadSize);

       //
       // Compute all CLA task vectors
       //
       EALLOW;
       Cla1Regs.MVECT1 = (Uint16)((Uint32)&Cla1Task1 -(Uint32)&Cla1Prog_Start);
       EDIS;

       //
       // Step 3 : Mapping CLA tasks
       // All tasks are enabled and will be started by an ePWM trigger
       // Map CLA program memory to the CLA and enable software breakpoints
       //
       EALLOW;
       Cla1Regs.MPISRCSEL1.bit.PERINT1SEL  = CLA_INT1_NONE;
       Cla1Regs.MPISRCSEL1.bit.PERINT8SEL  = CLA_INT8_NONE;
       Cla1Regs.MIER.all                   = 0x00FF;
       EDIS;
       // Call Flash Initialization to setup flash waitstates
       // This function must reside in RAM
       memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize);


       //Peripherals Initialization
       //I2C A initialization
       I2CA_Init();
//
//       // Initialize the SPI and SCI FIFO
       spi_init();
       spi_fifo_init();

       // Initialize SCI and SCI FIFO
       scia_echoback_init();
       scia_fifo_init();

       InitFlash();

       //Initialize ADXL Vibration Sensor
       ADXL_Init();
//
//       //Initialize LCD Display
       Rpm_Display_Init();

       //Initialize Ring Buffer to store sensor data
       ADXL_buffer_Init(&ADXL_ringBuffer_X, (Uint8*)test_input, sizeof(test_input));
       ADXL_buffer_Init(&ADXL_ringBuffer_Y, (Uint8*)test_inputY, sizeof(test_inputY));
       ADXL_buffer_Init(&ADXL_ringBuffer_Z, (Uint8*)test_inputZ, sizeof(test_inputZ));

       // Initialize Timers
       Timer_Init();          // Initialize Timer for Cyclic Interrupt

       // Initialize GPIO pin for push button to switch between 2 wheeler and 4 Wheeler
       init_button(pButton);
       memset(RPM, 0 ,sizeof(RPM));

       //
       // Enable CLA interrupts at the group and subgroup levels
       //
       PieCtrlRegs.PIEIER11.all       = 0xFFFF;
       IER |= (M_INT11 );
       EINT;       // Enable Global interrupt INTM
       ERTM;       // Enable Global realtime interrupt DBGM

       //
       // Switch the CLA program space to the CLA and enable software forcing
       // Also switch over CLA data ram 0,1 and 2
       // CAUTION: The RAMxCPUE bits can only be enabled by writing to the
       // register and not the individual bit field. Furthermore, the status of
       // these bitfields is not reflected in either the watch or register views -
       // they always read as zeros. This is a known bug and the user is advised
       // to test CPU accessibilty first before proceeding
       //
       EALLOW;
       Cla1Regs.MMEMCFG.all = 0xffff;
               //CLA_PROG_ENABLE|CLARAM0_ENABLE|CLARAM1_ENABLE|
                              //CLARAM2_ENABLE|CLA_RAM1CPUE;
       Cla1Regs.MCTL.bit.IACKE = 1;
       EDIS;

       //
       // Invoke Task(s)
       //
       //test_run();

       //
       // Report Results
       //
       //test_report();
    //Infinite Loop
    while(1)
    {

        FPU_FFT_Tick();
     }
}
//
// CLA ISRs
//
__interrupt void
cla1_task1_isr(void)
{
    PieCtrlRegs.PIEACK.bit.ACK11 = 1;
}
// End of File
//

int FPU_FFT_Tick()//this function is called in main to calculate fft
{
    // Locals
    Uint16 tempRPM=0;
    float fft_size = RFFT_SIZE;
    Uint16 RPM_4wheel_X = 0;
    Uint16 RPM_4wheel_Y = 0;
    Uint16 RPM_4wheel_Z = 0;
    static Uint16 j=0;
    {
        Uint16 i=0;
        for(i=0; i < RFFT_SIZE; i++){
            IOBuffer[i] = test_input[i];
        }
    }
    hnd_rfft->FFTSize   = RFFT_SIZE;
    hnd_rfft->FFTStages = RFFT_STAGES;
    hnd_rfft->InBuf     = &IOBuffer[0];  //Input buffer
    hnd_rfft->OutBuf    = &IOBuffer2[0];  //Output buffer

    hnd_rfft->MagBuf    = &RFFTmagBuff[0];  //Magnitude buffer

    hnd_rfft->CosSinBuf = &RFFTF32Coef[0];  //Twiddle factor buffer
    RFFT_f32_sincostable(hnd_rfft);         //Calculate twiddle factor

    {
        Uint16 i=0;
        for (i=0; i < RFFT_SIZE; i++){
            IOBuffer2[i] = 0;               //Clean up output buffer
        }
    }

    {
        Uint16 i=0;
        for (i=0; i <= RFFT_SIZE/2; i++){
            RFFTmagBuff[i] = 0;                //Clean up magnitude buffer
        }
    }
#ifndef USE_CLA
    RFFT_f32(hnd_rfft);                     //Calculate real FFT


    RFFT_f32_mag(hnd_rfft);                 //Calculate magnitude
#else
    test_run();
#endif
    //              hnd_rfft->PhaseBuf = &RFFTmagBuff[0];    //Use magnitude buffer
    {
        Uint16 i=1;
        for (i =1; i <= RFFT_SIZE/2; ++i)
        {
            if ((RFFTmagBuff[i] > maxMagnitude) )
            {  //&& (IOBuffer2[i] < 20)// && maxMagnitude < 40
                maxMagnitude = RFFTmagBuff[i];
                peakIndex = i;
            }
        }
    }
    frequency = (Fs * peakIndex) / (fft_size);
    if(maxMagnitude<3)
    {
        RPM_4wheel_X = 0;
    }
    else
    {
        RPM_4wheel_X= RPM_Value(frequency,4);
    }

    ////      RPM in Y AXIS
    {
        Uint16 i=0;
        for(i=0; i < RFFT_SIZE; i++){
            IOBuffer[i] = test_inputY[i];
        }
    }
    hnd_rfft->FFTSize   = RFFT_SIZE;
    hnd_rfft->FFTStages = RFFT_STAGES;
    hnd_rfft->InBuf     = &IOBuffer[0];  //Input buffer
    hnd_rfft->OutBuf    = &IOBuffer2[0];  //Output buffer
    hnd_rfft->MagBuf    = &RFFTmagBuff[0];  //Magnitude buffer
    hnd_rfft->CosSinBuf = &RFFTF32Coef[0];  //Twiddle factor buffer
    RFFT_f32_sincostable(hnd_rfft);         //Calculate twiddle factor
    {
        Uint16 i=0;
        for (i=0; i < RFFT_SIZE; i++){
            IOBuffer2[i] = 0;               //Clean up output buffer
        }
    }
    {
        Uint16 i=0;
        for (i=0; i <= RFFT_SIZE/2; i++){
            RFFTmagBuff[i] = 0;                //Clean up magnitude buffer
        }
    }
#ifndef USE_CLA
    RFFT_f32(hnd_rfft);                     //Calculate real FFT
    RFFT_f32_mag(hnd_rfft);                 //Calculate magnitude
#else
    test_run();
#endif
    //              hnd_rfft->PhaseBuf = &RFFTmagBuff[0];    //Use magnitude buffer
    {
        Uint16 i=1;
        for (i =1; i <= RFFT_SIZE/2; ++i)
        {
            if ((RFFTmagBuff[i] > maxMagnitude) )
            {
                maxMagnitude = RFFTmagBuff[i];
                peakIndex = i;
            }
        }
    }
    frequency = (Fs * peakIndex) / (fft_size);
    if(maxMagnitude<3)
    {
        RPM_4wheel_Y = 0;
    }
    else
    {
        RPM_4wheel_Y= RPM_Value(frequency,4);

    }
    //      RPM in Z AXIS
    {
        Uint16 i=0;
        for(i=0; i < RFFT_SIZE; i++){
            IOBuffer[i] = test_inputZ[i];
        }
    }
    hnd_rfft->FFTSize   = RFFT_SIZE;
    hnd_rfft->FFTStages = RFFT_STAGES;
    hnd_rfft->InBuf     = &IOBuffer[0];  //Input buffer
    hnd_rfft->OutBuf    = &IOBuffer2[0];  //Output buffer
    hnd_rfft->MagBuf    = &RFFTmagBuff[0];  //Magnitude buffer
    hnd_rfft->CosSinBuf = &RFFTF32Coef[0];  //Twiddle factor buffer
    RFFT_f32_sincostable(hnd_rfft);         //Calculate twiddle factor
    {
        Uint16 i=0;
        for (i=0; i < RFFT_SIZE; i++){
            IOBuffer2[i] = 0;               //Clean up output buffer
        }
    }
    {
        Uint16 i=0;
        for (i=0; i <= RFFT_SIZE/2; i++){
            RFFTmagBuff[i] = 0;                //Clean up magnitude buffer
        }
    }
#ifndef USE_CLA
    RFFT_f32(hnd_rfft);                     //Calculate real FFT
    RFFT_f32_mag(hnd_rfft);                 //Calculate magnitude
#else
    test_run();
#endif
    //              hnd_rfft->PhaseBuf = &RFFTmagBuff[0];    //Use magnitude buffer
    {
        Uint16 i=1;
        for (i =1; i <= RFFT_SIZE/2; ++i)
        {
            if ((RFFTmagBuff[i] > maxMagnitude) )
            {  //&& (IOBuffer2[i] < 20)// && maxMagnitude < 40
                maxMagnitude = RFFTmagBuff[i];
                peakIndex = i;
            }
        }
    }
    frequency = (Fs * peakIndex) / (fft_size);
    if(maxMagnitude<3)
    {
        RPM_4wheel_Z = 0;
    }
    else
    {
        RPM_4wheel_Z = RPM_Value(frequency,4);
    }

    if(((RPM_4wheel_X != RPM_4wheel_Y) && (RPM_4wheel_Y != RPM_4wheel_Z)))
    {
        return 1;
    }
    else if((RPM_4wheel_X != RPM_4wheel_Y) || (RPM_4wheel_Y != RPM_4wheel_Z) || (RPM_4wheel_X != RPM_4wheel_Y))
    {
        if((RPM_4wheel_X == RPM_4wheel_Y))
        {
            RPM_4wheel_Z = RPM_4wheel_Y;
        }
        else  if((RPM_4wheel_Z == RPM_4wheel_Y))
        {
            RPM_4wheel_X = RPM_4wheel_Y;
        }
        else  if((RPM_4wheel_Z == RPM_4wheel_X))
        {
            RPM_4wheel_Y = RPM_4wheel_X;
        }

        RPM[j] =RPM_4wheel_Z;// (RPM_4wheel_X + RPM_4wheel_Y + RPM_4wheel_Z)/3;
    }
    else
    {
        RPM[j] = RPM_4wheel_Z;//(RPM_4wheel_X + RPM_4wheel_Y + RPM_4wheel_Z)/3;
    }

    if((j >= 2) && ((RPM[j] - RPM[j-1]) > 30) && ((RPM[j]-RPM[j-2]) < 20))
    {
        RPM[j-1] = RPM[j];
    }
    if((j<2 && (RPM[1] - RPM[0])> 30) && ((RPM[1] - RPM[4])< 20))
    {
        RPM[0] = RPM[1];
    }
    j++;
//
    if(j>4) {j=0;}
    {
        Uint16 i=0;
        for(i=0;i<5;i++)
        {
            tempRPM += RPM[i];
        }
        tempRPM = tempRPM/5;
    }
    RPM_4wheel =tempRPM;
    maxMagnitude = 0;
    TTL_PULSE_FLAG =  true;
    // End of test
    //  done();
    // Execution never reaches this point
    return 1;
}

//###########################################################################
//
// TITLE:       divide.cla
//
// Description: Divide using Newton Raphson Approximation
//
//###########################################################################
// $TI Release:  $
// $Release Date:  $
// $Copyright:
// Copyright (C) 2009-2023 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "DSP28x_Project.h"

//
// Include the test header file whose name is based on the test name
// which is defined by the macro TEST on the command line
//
#include "divide_shared.h"
#include "cla_cfft.h"
//
// Cla1Task1 - Divide using a newton raphson approximation
//
__interrupt void
Cla1Task1 (void)
{
    Res = Num/Den;
    __mdebugstop();
    CLA_CFFT_run256Pt();

    // "Unpack" the 512 point complex spectrum to get half the
    // spectrum of the original (real only) data. The user may
    // use the conjugate symmetry property of the FFT of real
    // signals to determine the latter half of the spectrum
    __mdebugstop();
    CLA_CFFT_unpack256Pt();
}

//
// CLA ISRs
//
__interrupt void
Cla1Task2 (void)
{

}

__interrupt void
Cla1Task3 (void)
{
   
}

__interrupt void
Cla1Task4 (void)
{
   
}

__interrupt void
Cla1Task5 (void)
{
   
}

__interrupt void
Cla1Task6 (void)
{
   
}

__interrupt void
Cla1Task7 (void)
{
   
}

__interrupt void
Cla1Task8 (void)
{
   
}

//
// End of File
//

Hi Sanjay,

I don't see any immediate issues with your code, but I'll let you know next week if I find anything wrong. However, after consulting another CLA expert, I would recommend switching to a newer device like the F2837xD. There are hard-coded FFT examples in the CLA Math library and a dedicated section of ROM for the CLA in this device. The library examples can be found in [C2000ware install]\libraries\math\CLAmath\c28\examples. Let me know if this would be a better option for you.

Best Regards,

Delaney

Hello Delaney, I already followed the example you described. I am sometimes getting fft fixed value and sometimes random values. I have confusion, where to put the following sections:

FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD

FPUfftTables : > RAML456, PAGE = 1//ADDED
IOBuffer: > CLARAM2,ALIGN=2048, PAGE = 1
IOBuffer2: > CLARAM2,ALIGN=512, PAGE = 1
MagnitudeBuffer : > RAML456, PAGE = 1
TwiddleBuffer : > RAML456, PAGE = 1

As for now I have put IOBuffer sections in CLARAM2 as these buffers should be shared between c28 and CLA. Am I right, where should I put the other buffers like magnitude and twiddle factors, should they also be in shared ram like IOBuffers, and also let me know if something i missed in the cmd file or in my code which i uploaded in earlier post. I am not getting what to do. Also I saw some sites that these buffers should be aligned, is this right, Currently my IOBuffer is 256 floats size because I am calculating fft of 256 points(256 floats). What should be according to that?

Hi Sanjay,

This expert is currently on leave. Please allow for some delay in response until her return tomorrow.

Thanks & Regards,

Allison

Hi Sanjay,

Sorry for the delay. What addresses of memory are using for RAML456? I don't see it in the previous linker command file you sent. Keep in mind that on the F2806x the CLA doesn't have access to the LSRAM4 (and also doesn't have a LSRAM5 or LSRAM6). If you are mapping anything to those areas of memory, they cannot be accessed by the CLA and may be the cause of the issue you're seeing.

Generally, you should match what is included in the linker command file provided in C2000ware for the align and page attributes. For example, if those sections of memory are aligned there, they should be aligned in your file. 

Again, I would recommend switching to a newer device where these tables are already hardcoded into the ROM and there are examples doing what you are looking for, but it's up to you.  

Best Regards,

Delaney