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Original question:

CCS/TMS320F28379D: TMS320f28579D/EMIF/EtherCat

TMS320F28379D: EMIF1 Multiple Chip Parallel Operation with 8 bit & 16 bit Asynchronous Devices

Hafiz Haja
Intellectual 500 points

Part Number: TMS320F28379D

Hello,

We are using TMS320F28379D in one of our applications. EMIF1 module of TMS320F28379D to be interfaced to multiple Memory / Digital transceiver IC's as mentioned below:

1. With external 1M x 16 SRAM: EM1CS[2] + 16 bit data + EM1A[19]/EM1BA[1] (SRAM-A0) + EM1A[0:18] (SRAM[A1 : A19])

2. With external 16 bit Ethernet controller LAN91C111 (MAC + PHY) - EM1CS[3] + 16 bit data + EM1BA[1] (LAN-A0) + EM1A[0:14] (SRAM[A1 : A15]) + nWE

3. With external 8 bit Octal UART interface chip: EM1CS[4] + 8 bit data + EM1BA[1:0] (UART-A[1:0]) + EM1A[0] (UART[A2]) + nWE

Query 1: Please confirm whether the above hardware requirement is possible because this circuit requires switching of EMIF mode from 16 bit to 8 bit and vice versa.

Query 2: As per datasheet Table 6-4, EMIF1_CSxn is defined with fixed start address & end address. For memory devices this seems ok. For other asynchronous devices such as Ethernet controller & UART transceiver will there be any issues? Because CPU should be able to access registers / read or write data from or to these Digital transceivers.

Regards

Hafiz Haja

  • 0
    TI__Mastermind 30185 points

    Hello Hafiz,

    Hafiz Haja said:
    Query 1: Please confirm whether the above hardware requirement is possible because this circuit requires switching of EMIF mode from 16 bit to 8 bit and vice versa.

    Your setup looks mostly fine based on your distribution of address lines and synchronous/asynchronous chip selects, but why does 1 have EM1A[19] and EM1BA[1] together? Are you actually planning to use both pins for this particular access or is it just because they share the same GPIO pin? I want to make sure I understand the intention behind this.

    Hafiz Haja said:
    Query 2: As per datasheet Table 6-4, EMIF1_CSxn is defined with fixed start address & end address. For memory devices this seems ok. For other asynchronous devices such as Ethernet controller & UART transceiver will there be any issues? Because CPU should be able to access registers / read or write data from or to these Digital transceivers.

    It should be fine as long as you access the asynchronous devices with valid addresses. You will be treating these communication devices as external memories, so within your software you will need to make sure you are providing valid addresses to access the appropriate registers. The verification of the address here will need to come from the software itself.

  • 0 in reply to Omer Amir
    Intellectual 500 points

    Hello,

    Why does 1 have EM1A[19] and EM1BA[1] together?

    As you said, it is just because they share the same GPIO pin.

    Regards

    Hafiz

  • 0 in reply to Hafiz Haja
    TI__Mastermind 30185 points

    Hello Hafiz,

    Understood, then from what I see in your description the hardware setup looks fine.