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TMS320F28379D: interrupt nesting

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE
Hello TI expert,
1. In my application, I am using multiple peripherals like EPWM, SDFM, ADC, EQEP, ECAP, CAN. And, I would like to nest interrupts for some peripherals. What is the max no. of interrupts that can be nested so that when ISR is executed there's no stack overflow due to multiple nesting. Is there a limit to no. of interrupts that can be nested?
2. I'm trying out the swprioritized_interrupts example to understand interrupt nesting. I've read the documentation, https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html. By changing the INTxPL and Gx_yPL values shown below in F2837xD_SWPrioritizedIsrLevels.h header, priorities can be changed from which a mask value is automatically generated by sw_interrupt_prioritization_logic.h during compilation.
  
My question is how the mask values are directly calculated and assigned to IER and PIEIER in the below example. Can you elaborate on the sample mask calculation. (M_INT2, MINT2). 
3. Where can i find the DSP28_SWPrioritizedIsrLevels.h mentioned in https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html ?
4. Just to clarify: I am using software interrupts nesting, I am making EPWM priority=1 and ADC priority=2. If I receive interrupts from both groups simultaneously, then according to hardware priority, ADC ISR will be entered first. But inside the ADC ISR function, as i am defining:
        IER |= 0x003;                        // Set global priority by adjusting IER
        IER &= 0x003;    (enabling EPWM interrupt)
the ADC ISR gets pushed to stack and the EPWM ISR will execute now. After the EPWM ISR gets executed ADC ISR will continue now. Is my understanding correct?


Thanks in advance!