• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 82 subscribers
  • Views 477 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS320F28377D: boot status do not tell me reset cause，how to do

TMS320F28377D: How does boot status reflect the reset cause

?? ?
Prodigy 10 points
Part Number: TMS320F28377D


Hello.
I had the same problem when I was working on a project.
I use CCS for debugging. I stop feeding dog in CPU2, the process will stop automatically. After using the "CPU Reset" and "Restart" buttons on CCS to reload the program (without power failure) again, I can get that the WDRSn bit (bit 2) is 1 in the SYSCTL_O_RESC register. 

This does correspond to the watchdog reset problem. As mentioned in section 4.10.11.13 of the technical manual, I believe that after the chip is repowered, even though the SYSCTL_O_RESC register will be reset,  bit 22 in "CPU2 Boot ROM Status" at address 0x0000 0002 should be set to 1 to reflect the CPU2 watchdog reset.

But in my actual test, after the chip was powered back on, I read the "CPU2 Boot ROM Status", but bit 22 didn't match expectations.

I was very confused

  • 0
    TI__Expert 8581 points

    Hi,

    The reset cause bits get cleared for both SYSCTL_O_RESC and CPU2 Boot ROM status bits during a power on reset.

    I am not able to find the particular section that you have pointed out - section 4.10.11.13. Please have a look at the latest TRM for more details,

    Thanks

    Aswin

  • 0
    TI__Expert 8581 points

    Hi,

    ?? ? said:
    As mentioned in section 4.10.11.13 of the technical manual, I believe that after the chip is repowered, even though the SYSCTL_O_RESC register will be reset,  bit 22 in "CPU2 Boot ROM Status" at address 0x0000 0002 should be set to 1 to reflect the CPU2 watchdog reset.

    Can you please have a look at the latest TRM and point me to the location where you have found out this details,

    I understand that SYSCTL_O_RESC register will be undergo reset, similar should be the case for CPU2 Boot ROM status bits also during a power on reset.

    Thanks

    Aswin