TMS320F280049C: Interleaved Totem Pole PFC Peak Current Mode Conrol

Hi,

I want to perform peak current mode control for interleaved totem pole pfc. I set the CMPSS1 and CMPSS2. CMPSS1 is for inductor current of one phase in the totem pole PFC. CMPSS2 is for inductor current of the other phase of the totem pole PFC. When the grid is positive, high comparator of CMPSS1 and CMPSS2 is active. When the grid is negative, low comparator of CMPSS1 and CMPSS2 is active. Since the low comparator is active in negative grid current, I invert the output of low comparator. CMPSS1 is synchronous with EPWM2. CMPSS2 is synchronous with EPWM3.

In EPWM modules, I set similar like in CMPSS modules. There are different settings for negative and positive grid voltage. For the positive grid voltage, EPWMB is master for trip zone. For the negative grid voltage, EPWMA is master for trip zone. For dead band module, T1 trigger is used for EPWMA trip zone in negative grid voltage and T2 trigger is used for EPWMB trip zone in positive grid voltage. I use individually Digital Compare A and B event 2 for positive and negative grid voltage. Also, for synchronization with CMPSS modules, HRPCTL register is set for COMPC_UP. Also, I swap the PWMs with 100kHz ISR in grid zero crossing regions

But, my code do not work. My CMPSS and EPWM settings is like following. 

Could you please check my code ? 

void setupPCMCCMPSS(void)
{

CMPSS_enableModule(CMPSS1_BASE);
CMPSS_enableModule(CMPSS2_BASE);
//
// Use ramp generator for NEG input and configure the CMPSS output
//
CMPSS_configHighComparator(CMPSS1_BASE,CMPSS_INSRC_DAC);
CMPSS_configHighComparator(CMPSS2_BASE,CMPSS_INSRC_DAC);
CMPSS_configLowComparator(CMPSS1_BASE,CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);
CMPSS_configLowComparator(CMPSS2_BASE,CMPSS_INSRC_DAC | CMPSS_INV_INVERTED);

ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1, 1);
ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_2, 3);
ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1, 1);
ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_2, 3);

// Use VDDA as the reference for comparator DACs
//
CMPSS_configDAC(CMPSS1_BASE,(CMPSS_DACVAL_PWMSYNC | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW));
CMPSS_configDAC(CMPSS2_BASE,(CMPSS_DACVAL_PWMSYNC | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW));

CMPSS_configureSyncSource(CMPSS1_BASE, 3);
CMPSS_configureSyncSource(CMPSS2_BASE, 4);

CMPSS_setDACValueHigh(CMPSS1_BASE,2209);
CMPSS_setDACValueHigh(CMPSS2_BASE,2209);
CMPSS_setDACValueLow(CMPSS1_BASE,2209);
CMPSS_setDACValueLow(CMPSS2_BASE,2209);

CMPSS_configOutputsHigh(CMPSS1_BASE, CMPSS_TRIP_ASYNC_COMP | CMPSS_TRIPOUT_ASYNC_COMP);
CMPSS_configOutputsHigh(CMPSS2_BASE, CMPSS_TRIP_ASYNC_COMP | CMPSS_TRIPOUT_ASYNC_COMP);
CMPSS_configOutputsLow(CMPSS1_BASE, CMPSS_TRIP_ASYNC_COMP | CMPSS_TRIPOUT_ASYNC_COMP);
CMPSS_configOutputsLow(CMPSS2_BASE, CMPSS_TRIP_ASYNC_COMP | CMPSS_TRIPOUT_ASYNC_COMP);
//
// Enable the clearing of the CMPSS high latch every ePWM cycle.
// Read the CMPSS low latch clear setting in order to preserve
// its preexisting setting.
CMPSS_clearFilterLatchHigh(CMPSS1_BASE);
CMPSS_clearFilterLatchHigh(CMPSS2_BASE);
CMPSS_clearFilterLatchLow(CMPSS1_BASE);
CMPSS_clearFilterLatchLow(CMPSS2_BASE);

}

void setup_ILC_PFC_FBPWM(void)
{

// Time Base SubModule Registers
EPWM_setPeriodLoadMode(EPWM1_BASE,EPWM_PERIOD_SHADOW_LOAD);
EPWM_setTimeBasePeriod(EPWM1_BASE, 999);
EPWM_setTimeBaseCounter(EPWM1_BASE,0);
EPWM_setPhaseShift(EPWM1_BASE,0);
EPWM_setTimeBaseCounterMode(EPWM1_BASE,EPWM_COUNTER_MODE_UP);
EPWM_setClockPrescaler(EPWM1_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);

// Counter Compare Submodule Registers
// set duty 0% initially
EPWM_setCounterCompareValue(EPWM1_BASE,EPWM_COUNTER_COMPARE_A,2);

EPWM_disableCounterCompareShadowLoadMode(EPWM1_BASE,EPWM_COUNTER_COMPARE_A);

// to start don't configure the PWM to do anything
HWREGH(base1 + EPWM_O_AQCTLA) =0 ;

EPWM_setPeriodLoadMode(EPWM2_BASE,EPWM_PERIOD_SHADOW_LOAD);
EPWM_setTimeBasePeriod(EPWM2_BASE,999);
EPWM_setTimeBaseCounter(EPWM2_BASE,0);
EPWM_setPhaseShift(EPWM2_BASE,0);
EPWM_setTimeBaseCounterMode(EPWM2_BASE,EPWM_COUNTER_MODE_UP);
EPWM_setClockPrescaler(EPWM2_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);

EPWM_setPeriodLoadMode(EPWM3_BASE,EPWM_PERIOD_SHADOW_LOAD);
EPWM_setTimeBasePeriod(EPWM3_BASE,999);
EPWM_setTimeBaseCounter(EPWM3_BASE,0);
EPWM_setPhaseShift(EPWM3_BASE,0);
EPWM_setTimeBaseCounterMode(EPWM3_BASE,EPWM_COUNTER_MODE_UP);
EPWM_setClockPrescaler(EPWM3_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);

// to start don't configure the PWM to do anything
HWREGH(base2 + EPWM_O_AQCTLA) =0 ;
HWREGH(base3 + EPWM_O_AQCTLA) =0 ;

//
EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_A , EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A , EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

// CTR = ZERO , set to 0
//
EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_B , EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_B , EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);

//
// CTR = T2U , set to 1
//
EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_A , EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(EPWM2_BASE, EPWM_AQ_OUTPUT_B , EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP);

EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_A , EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T1_COUNT_UP);
EPWM_setActionQualifierAction(EPWM3_BASE, EPWM_AQ_OUTPUT_B , EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_T2_COUNT_UP);

EPWM_setActionQualifierT1TriggerSource(EPWM2_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2);
EPWM_setActionQualifierT2TriggerSource(EPWM2_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2);
EPWM_setActionQualifierT1TriggerSource(EPWM3_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2);
EPWM_setActionQualifierT2TriggerSource(EPWM3_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2);

XBAR_enableEPWMMux(XBAR_TRIP5, 0x00);
XBAR_enableEPWMMux(XBAR_TRIP7, 0x00);

//
// Select CMPSS trip signal from ePWM XBAR as source for DCAH
//
XBAR_setEPWMMuxConfig(XBAR_TRIP5, XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L);
XBAR_setEPWMMuxConfig(XBAR_TRIP7, XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L);

XBAR_enableEPWMMux(XBAR_TRIP5, XBAR_MUX00);
XBAR_enableEPWMMux(XBAR_TRIP7, XBAR_MUX02);

EPWM_selectDigitalCompareTripInput(EPWM2_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCAH);
EPWM_selectDigitalCompareTripInput(EPWM2_BASE, EPWM_DC_TRIP_TRIPIN5, EPWM_DC_TYPE_DCBH);
EPWM_selectDigitalCompareTripInput(EPWM3_BASE, EPWM_DC_TRIP_TRIPIN7, EPWM_DC_TYPE_DCAH);
EPWM_selectDigitalCompareTripInput(EPWM3_BASE, EPWM_DC_TRIP_TRIPIN7, EPWM_DC_TYPE_DCBH);

EPWM_setTripZoneDigitalCompareEventCondition(EPWM2_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(EPWM2_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_BASE, EPWM_TZ_DC_OUTPUT_A2, EPWM_TZ_EVENT_DCXH_HIGH);
EPWM_setTripZoneDigitalCompareEventCondition(EPWM3_BASE, EPWM_TZ_DC_OUTPUT_B2, EPWM_TZ_EVENT_DCXH_HIGH);

EPWM_setDigitalCompareEventSource(EPWM2_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
EPWM_setDigitalCompareEventSource(EPWM3_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
EPWM_setDigitalCompareEventSource(EPWM2_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);
EPWM_setDigitalCompareEventSource(EPWM3_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL);

EPWM_setDigitalCompareEventSyncMode(EPWM2_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
EPWM_setDigitalCompareEventSyncMode(EPWM3_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
EPWM_setDigitalCompareEventSyncMode(EPWM2_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);
EPWM_setDigitalCompareEventSyncMode(EPWM3_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_2, EPWM_DC_EVENT_INPUT_NOT_SYNCED);

EPWM_enableTripZoneSignals(EPWM2_BASE, EPWM_TZ_SIGNAL_DCAEVT2 | EPWM_TZ_SIGNAL_DCBEVT2);
EPWM_enableTripZoneSignals(EPWM3_BASE, EPWM_TZ_SIGNAL_DCAEVT2 | EPWM_TZ_SIGNAL_DCBEVT2);

EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
EPWM_setTripZoneAction(EPWM2_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);
EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW);
EPWM_setTripZoneAction(EPWM3_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW);

EPWM_selectCycleByCycleTripZoneClearEvent(EPWM2_BASE, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);
EPWM_selectCycleByCycleTripZoneClearEvent(EPWM3_BASE, EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD);

EPWM_clearTripZoneFlag(EPWM2_BASE, (EPWM_TZ_INTERRUPT_OST | EPWM_TZ_SIGNAL_DCBEVT1));
EPWM_clearTripZoneFlag(EPWM3_BASE, (EPWM_TZ_INTERRUPT_OST | EPWM_TZ_SIGNAL_DCBEVT1));

// Dead band generator
EPWM_setDeadBandControlShadowLoadMode(EPWM2_BASE, EPWM_DB_LOAD_ON_CNTR_ZERO);
EPWM_setDeadBandControlShadowLoadMode(EPWM3_BASE, EPWM_DB_LOAD_ON_CNTR_ZERO);

EPWM_setRisingEdgeDelayCountShadowLoadMode(EPWM2_BASE, EPWM_RED_LOAD_ON_CNTR_PERIOD);
EPWM_setRisingEdgeDelayCountShadowLoadMode(EPWM3_BASE, EPWM_RED_LOAD_ON_CNTR_PERIOD);

EPWM_setFallingEdgeDelayCountShadowLoadMode(EPWM2_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);

EPWM_setFallingEdgeDelayCountShadowLoadMode(EPWM3_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO);

//
// Active high complementary PWMs - Set up the deadband
//
EPWM_setDeadBandCounterClock(EPWM2_BASE, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
EPWM_setRisingEdgeDelayCount(EPWM2_BASE, 50);
EPWM_setFallingEdgeDelayCount(EPWM2_BASE, 50);
EPWM_setDeadBandDelayMode(EPWM2_BASE, EPWM_DB_RED, true);
EPWM_setDeadBandDelayMode(EPWM2_BASE, EPWM_DB_FED, true);
EPWM_setRisingEdgeDeadBandDelayInput(EPWM2_BASE, EPWM_DB_INPUT_EPWMA);
EPWM_setFallingEdgeDeadBandDelayInput(EPWM2_BASE, EPWM_DB_INPUT_EPWMA);
EPWM_setDeadBandDelayPolarity(EPWM2_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
EPWM_setDeadBandDelayPolarity(EPWM2_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);

EPWM_setDeadBandCounterClock(EPWM3_BASE, EPWM_DB_COUNTER_CLOCK_FULL_CYCLE);
EPWM_setRisingEdgeDelayCount(EPWM3_BASE, 50);
EPWM_setFallingEdgeDelayCount(EPWM3_BASE, 50);
EPWM_setDeadBandDelayMode(EPWM3_BASE, EPWM_DB_RED, true);
EPWM_setDeadBandDelayMode(EPWM3_BASE, EPWM_DB_FED, true);
EPWM_setRisingEdgeDeadBandDelayInput(EPWM3_BASE, EPWM_DB_INPUT_EPWMA);
EPWM_setFallingEdgeDeadBandDelayInput(EPWM3_BASE, EPWM_DB_INPUT_EPWMA);
EPWM_setDeadBandDelayPolarity(EPWM3_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
EPWM_setDeadBandDelayPolarity(EPWM3_BASE, EPWM_DB_RED, EPWM_DB_POLARITY_ACTIVE_HIGH);

EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);

EPWM_enablePhaseShiftLoad(EPWM2_BASE);
EPWM_setSyncOutPulseMode(EPWM2_BASE, EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);
EPWM_setPhaseShift(EPWM2_BASE, 2 );
EPWM_setCountModeAfterSync(EPWM2_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);

EPWM_enablePhaseShiftLoad(EPWM3_BASE);
EPWM_setSyncOutPulseMode(EPWM3_BASE, EPWM_SYNC_OUT_PULSE_ON_SOFTWARE);

//
// 3-Ph Interleaving Register Setting
//
EPWM_setPhaseShift(EPWM3_BASE, (2 + 500);
EPWM_setCountModeAfterSync(EPWM3_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);

EPWM_setSyncPulseSource(EPWM2_BASE, HRPWM_PWMSYNC_SOURCE_COMPC_UP);
EPWM_setCounterCompareValue(EPWM2_BASE, EPWM_COUNTER_COMPARE_C, 5);
EPWM_setSyncPulseSource(EPWM3_BASE, HRPWM_PWMSYNC_SOURCE_COMPC_UP);
EPWM_setCounterCompareValue(EPWM3_BASE, EPWM_COUNTER_COMPARE_C, 5);

EPWM_setActionQualifierContSWForceShadowMode(EPWM1_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO);
EPWM_setActionQualifierContSWForceShadowMode(EPWM2_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO);
EPWM_setActionQualifierContSWForceShadowMode(EPWM3_BASE, EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO);
}