TMS320F28377D: PWM Action-Qualifier Event Priority

Hi Huihuang, 

Firstly, which document you get this table from? I believe this TRM table has been updated to get rid of redundant rows 9 and 10. The current revision of the TRM document for this device shows the following:

The rows 9 and 10 do not apply because the moment the counter hits '0' (for up-down count), the counter direction is set to be "incrementing". Hence, CMPBD and CMPAD are no longer applicable. Conversely, when the counter is at TBPRD (for up-down count), the counter direction is set to be "decrementing". Hence, CMPBU and CMPAU do not apply. Note that the same can be said of T1/T2 in rows 7 and 8 (rows 7 and 8 will be omitted in future versions of the document).

Now let me also try to clarify your confusion: If level 4 action and level 6 action occur on the same event, the higher priority action will be the one that is implemented (level 4 action). 

Case 1:

If CMPB = 3000 and you have the following action qualifiers:

• CMPBU = clear
• CMPBD = set
• CTR PRD = clear

When the counter is equal to PRD, there are two action qualifier events in contention (CMPBD and a CTR = PRD match). Note that CMPBU is not relevant because the counter is now in the state of "counting down" from PRD, not "counting up". 

This is where the prioritization comes in. The action that occurs at this moment will be the action sources from the event with higher priority. In this case, we can see from the table that a CMPBD match event has higher priority than a CTR = PRD event. So the PWM should follow CMPBD and set. 

Case 2:

If CMPB = 0 and you have the following action qualifiers:

• CMPBU = clear
• CMPBD = set
• CTR ZERO = set

When the counter is equal to 0, there are two action qualifier events in contention (CMPBU and a CTR = 0 match). Note that CMPBD is not relevant because the counter is now in the state of "counting up" from 0, not "counting down". 

This is where the prioritization comes in. The action that occurs at this moment will be the action sources from the event with higher priority. In this case, we can see from the table that a CMPBU match event has higher priority than a CTR = 0 event. So the PWM should follow CMPBU and clear.

Note that in general you should be careful if trying to set CMPx values to be 0 or period. If it is 0 or 100% duty that you are trying to target, please see this app note (https://www.ti.com/lit/an/spraai1/spraai1.pdf) for details on how to achieve this.

Best Regards,

Allison

Hi Huihuang,

1. As I listed in my prior response:

Allison Nguyen said:

Note that the same can be said of T1/T2 in rows 7 and 8 (rows 7 and 8 will be omitted in future versions of the document).

So you can ignore rows 7 and 8.

2. These cases are a bit strange. I think the main thing to focus on is that only one action should take place per event (hence, the need for the prioritization tables to tell you what will occur in the case of two actions configured for the same event). If actions are configured to take place on different events (e.g. different counter values), then they will occur independently.

The cases (1 and 2) that you mention have more to do with asking about the role of shadow loading. Please take a look at the application note I linked that has examples of using shadow loading for CMPA to achieve 0-100% duty cycle. This also can help to understand the role of shadow loading here. There is also a note in the TRM suggesting to avoid shadow loading on a CMPx=0 boundary condition. Please also double check the TRM descriptions to further clarify your understanding

3.

Huihuang Chen said:

By the way, for below table "Compare on Up-Count Event CAD/CBD"  they have mistake or not? need to change to "Compare on Up-Count Event CAU/CBU "or not?

^ Yes, you are correct. I just filed this typo to be updated in future releases. 

Best Regards,

Allison

Hi Huihuang,

Through the cases you listed, it sounds like you are asking the question of whether the CMPx values are loaded before or after the action occurs. The shadow loading should occur before the action takes place. For this to happen, you should be sure to write to the CMPA/B registers before the loading event (in case 1, loading event is CTR=PRD; in case 2, loading event is CTR=PRD), so CTR=1000 would be an ok time to write since it is well before these.

If the CMPA/B value is greater than your period value, the action will not occur because that CMPB value will never be reached. So in both cases, when you hit CTR=3000, only the action specified for TBPRD (clear) should occur. 

Note that the action qualifier module functions on clock edges, so you should not be able to have 2 actions occurring on the same edge, hence the priority.

Best Regards,

Allison

Hi Huihuang,

• The conclusion is that the CTR = period action will occur in both cases.
• Keep in mind this is because the intial value of CMPx is set to a normal value (less than the PRD, but not =0). Hence, the loading of the new CMPx value (3001 or 0) does not occur before the CTR = period action is carried out, and is therefore not prioritized over a CTR = PRD action for the first cycle where it needs to shadow load.

Below are results for testing this:

Parameters:

• PRD = 3000
• Up/down count mode
• CMPA is initialized to 1000
• EPWM1A actions:
  • CTR = 0 --> high
  • CTR = CMPAU --> low
  • CTR = CMPAD --> low
  • CTR = PRD --> high
• EPWM1B actions:
  • CTR = 0 --> low
  • CTR = PRD --> high

Case 1:

• ISR on CTR = 0 updates CMPA to be 3001 (shadow load on 0 or period)
• RESULT: EPWM1A sets high on CTR = period (follows the CTR = PRD action qualifier)
  • This holds true for the first EPWM period following the first interrupt. Note that the CMPA event action (low) is prioritized over following PRD event actions (high) since the CMPA value has been previously loaded.

• Ch1 (yellow) = EPWM1A
• Ch2 (blue) = EPWM1B
• Ch3 (purple) = GPIO2 toggled in EPWM ISR that updates CMPA

Case 2:

• ISR on CTR = 0 updates CMPA to be 0 (shadow load on 0 or period)
• RESULT: EPWM1A sets high on CTR = period (follows the CTR = PRD action qualifier)
  
  • Note that the CMPA event action (low) is prioritized over following 0 events (high).

• Ch1 (yellow) = EPWM1A
• Ch2 (blue) = EPWM1B
• Ch3 (purple) = GPIO2 toggled in EPWM ISR that updates CMPA

I've attached the code/project I used to test this.

E2E_EPWM_CMPA_update.zip

Best Regards,

Allison

Hi Huihuang,

Huihuang Chen said:

If CMPB >=  TBPRD, at the TBCTR = TBPRD moment , three event (CTR=CMPBU,CTR=CMPBD,CTR=TBPRD) will happen, but the actually action of AQ will be following below table priority, that means CMPBD will with the highest priority, so actual PWM output will will follow CMPBD  AQ setting .

Correction:

If CMPB is already set to a value greater than or equal to TBPRD, at the TBCTR = TBPRD moment, TWO match events (CTR = CMPBD match, CTR = TBPRD match) will technically occur. Only ONE action will occur on the PWM output (which is determined by the Action Qualifier event priority table). This means CMPBD will have the highest priority, so the output will follow CMPBD settings. This can again be very easily seen/tested using the project I attached and changing the CMPA value of the project. And this is actually already showcased in "Case 1" of my testing above if you look at Ch1 behavior after the CMPA value is shadow loaded to 3001.

Note that as soon as the counter = TBPRD, the count direction is "decrementing" (as shown by the top-right cell label of the Action Qualifier event priority table). As we discussed earlier in this thread, the bottom rows (rows 7-10) are removed in future revisions of the table as they are not applicable. 

Best Regards,

Allison