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Tool/software:
Input Voltage: 12V
PWM Duty Cycle: 50%
Under these conditions, the voltage of the transformer input pulse at the LV side is +- 100V, resulting in the FET failure. It seems that the FET is damaged because the FET's Vds is 80V, but pulses exceeding 100V are occurring. When simulated with PSIM, the output is +-12V, but the board I have made outputs +-100V. I would appreciate any help in understanding why this is happening.
