TMS320F28388D: tolerance of internal pull down

Obinna Ezeilo

Part Number: TMS320F28388D

Tool/software:

Hi ,

Referring to a previous post: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1358929/tms320f28388d-bga-package-layout-guidance

The datasheet states "There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled." but doesn't give an indication of the tolerance of this pulldown.

Customer had a separate question regarding internal pull-downs on the analog inputs ADCINA0, ADCINA1, and ADCINB1. The datasheet states that they are a 50kOhm nominal value, but doesn't give a range.

What's the expected tolerance of this internal pulldown?

Thanks, and regards,

Obinna.

over 1 year ago

0 Joseph Casuga over 1 year ago

TI__Mastermind 38140 points

Hi Obinna,

The 50KΩ internal pulldown is not well controlled impedance. This is the typical value and varies with process. I'll try to dig into some characterization and simulation data to see how this impedance varies.

Regards,

Joseph

0 Obinna Ezeilo over 1 year ago in reply to Joseph Casuga

TI__Intellectual 2395 points

Hi Joseph,

Thank you. Please let me know the outcome of your further investigation.

Regards,

Obinna.

0 Joseph Casuga over 1 year ago in reply to Obinna Ezeilo

TI__Mastermind 38140 points

Hi Obinna,

Char data and simulations show that the tolerance on the DAC pulldown is 50KΩ +/- 25% over process, voltage and temperature. Range would be from 37.5KΩ to 62.5KΩ.

Best regards,

Joseph

0 Obinna Ezeilo over 1 year ago in reply to Joseph Casuga

TI__Intellectual 2395 points

Hi Joseph,

One more question: customer is using EPWM outputs 3, 4, 5, and 6, but they're seeing some signal integrity concerns because the output impedance of the drivers on GPIO6, 8-10 is 70 Ohms, which isn't feasible to match with standard PCB technology traces.

They don't need high speed edges (the signal is only 500kHz max), but they want to prevent stair-stepping from reflections that could produce inconsistent behavior at the load. Is there some way to limit the slew rate of these drivers or otherwise minimize reflections?

Regards, Obinna.

0 Joseph Casuga over 1 year ago in reply to Obinna Ezeilo

TI__Mastermind 38140 points

Hi Obinna,

EPWM pins (or GPIOs for that matter) do not have slew rate control. Adding capacitors on the EPWM pins would help avoid the high speed edges. Maybe that is one recommendation we can offer to customer.

Regards,

Joseph

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TMS320F28388D: tolerance of internal pull down