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TMS320F2812: clock, PLL, crystal

Part Number: TMS320F2812


Tool/software:

Dear Team,

I am using TMS320F2812 DSP. Crystal 30MHZ, PLLCR=0x000A (i.e 5x), Clock 150MHZ, and XCLKOUT(pin-119) = 75MHZ.

But sometimes during power on condition, XCLKOUT showing only 15MHZ. i.e half of crystal value.

I am providing desired delay of 131072 cycles delay after writing to PLLCR register. 

I am stuck at this problem. please explain role of XPLLDIS, XRS, TRST pins role on this problem.

please help me to resolve this. 

Thanks alot,

Praveen Vemula.

  • Hi Praveen,

    If PLLCR is 0xA which mean CLKIN should be XTAL frequency.

    If PLL is disabled X1/XCLKIN is passed on as it is,
    If PLL is bypassed X1/XCLKIN is divided by /2 and passed out, and

    If PLL is enabled, it takes PLLCR selection bits and /2 and passed out.


    Thanks

  • Hi Prathan,

    I think you are completely mistaken. 

    your statement "If PLLCR is 0xA which mean CLKIN should be XTAL frequency." is wrong

    see highlighted bit description 1010=A, which means OSCLK*10/2 means clock frequency is 5 times of crystal frequency, as per my first post dtd. 29.Aug.2024. 

    my problem has been resolved after making following changes:

    1. pull up XPPLDIS pin

    2. pull down TRST pin.

    Thanks,

    Praveen Vemula.