TMS320F28388D: How to import more than eight input signals in a CLB tile

Hi Luke,

For the design that I have stated in the description, for 2 legs and one phase, I need:
1. 8 signals for switches shown in the picture because 4 signals (S1, S1C, S3 and S3C) for both legs are common. These 8 signals are required to be overridden and therefore, required for PWM protection.

2. 4 signals. In this, two signals are trip signals, 1 is HWCL enable signal, PWM enable signal. These signals will help to decide if the tripping needs to be done. 

3. 1 signal for sine reference polarity. This is required to make decisions regarding which signals need to be compared when the sine reference is in positive half region or negative half region. 

Eight PWM signals (in one phase and one leg) need to be overridden using below decision flow chart.

Same signals are to be repeated for other two phases as well.

Could you please help me to bring out the best utilization with 8 available CLB tiles in F28388D?

Beside this, I am concerned about number of PWM signals that could be overridden by a CLB tile. From my understanding, 2 PWM signals could be processed through one CLB tile (From - CLB Output Signal Multiplexer Table in TRM). That way, I could only process 16 PWM signals only. However, for 3L-ANPC use case, 24 PWM signals require PWM Protection through CLB tiles. Please help me to get a clarification on this as well.

Hey Rohit,

Let me suggest a simpler approach.

Instead of feeding all of your PWMs into the CLBs and using the LUTs to trip the PWMs, could you instead just generate the trip signal you need from the CLB, route this trip signal to a GPIO via CLB Output XBAR, and then use the inputxbar to trip all of the PWMs?

Thank you,

Luke

Hi Luke,

In some manner, I used this approach. 
I combined all HWCL trip signals with two CLB tiles to generate one trip signal for each phase and instead of routing it to a GPIO, I fed that as an input to another CLB tile. Below is an image of one of those two CLB tiles, that combine HWCL Signal to Phase A.

If you see in the image above, SINE_REF_POLARITY and PWM_ENABLE Signals are not combined because I could not see how these two would fit with remaining HWCL signals.
So, in total, I need 6 PWM Signals for state determination, the combined HWCL_ENABLE_SIGNAL generated in the tile above, SINE_REF_POLARITY and PWM_ENABLE Signal (9 Input signals). This is again, one more than the upper limit of 8 input signals.

Is this what you meant? If not, could you please explain more on your last comment. Thank you!

Hi Luke,

I am still feeding those PWM outputs to PWM because I need to determine the state of the signals that depends on each other in stages. For example, during trip action, when the sine is in positive region, I would compare if PWM signals S1 and S2 are high, if yes, then turn on the S2 signal for deadtime and later turn off remaining PWM signals S1, S2C, S3, S3C and S1C at the same time. If S1 and S2 are not high, then compare S1C and S2 PWM signals and take action further. This is an example of many examples. The states have to be decided and therefore multiple PWM signals are required to be compared. 

Again, thanks for an idea of ORring signals using CLB XBAR. This may help.

Hi Luke,

Sure! Allow me a week time to return on this. Meanwhile, I may share a final design based on what we have learnt so far and then we'd definitely go for a call.

Thank you!

Hi Rohit,

Understood, looking forward to your reply.

--Luke