Tool/software:
Hi,
I recently began exploring the F280025 Launchpad and am trying to understand the clock unit. Everything functions as expected until I completely erase the flash memory. After erasing, the external crystal no longer works, and there is no signal at the crystal's pin even after powering off and on. I would greatly appreciate any assistance in figuring out this issue. Thank you in advance!
Here is the code for reference:
#include "F28002x_Device.h" // Device-specific header file
void SysControl(void);
void delay(volatile long count);
void main(void)
{
// Step 1. Initialize System Control:
// Disable the Watchdog Timer
EALLOW;
WdRegs.WDCR.all = 0x68; // Disable watchdog
EDIS;
SysControl();
// Step 2. Initialize GPIO:
EALLOW; // Enable EALLOW protected register access
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 0U; // Set GPIO31 as GPIO
GpioCtrlRegs.GPADIR.bit.GPIO31 = 1U; // Set GPIO31 as output
EDIS; // Disable EALLOW protected register access
// Step 3. Toggle GPIO31 in an infinite loop
while(1)
{
GpioDataRegs.GPATOGGLE.bit.GPIO31 = 1U; // Toggle GPIO31
delay(50000);
}
}
void SysControl(void)
{
EALLOW;
// Step 1: Configure the clock source
ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 00U; // Choose external oscillator
delay(5000);
// Step 2: Configure the PLL for 100 MHz PLLSYSCLK
// Set the reference divider (REFDIV), multiplier (IMULT), and output divider (ODIV)
ClkCfgRegs.SYSPLLMULT.bit.REFDIV = 1U; // Reference divider value (REFCLK = XTAL / (REFDIV + 1))
ClkCfgRegs.SYSPLLMULT.bit.IMULT = 40U; // Integer multiplier value (IMULT)
ClkCfgRegs.SYSPLLMULT.bit.ODIV = 4U; // Output divider (ODIV)
// Step 3: Enable the PLL
ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1U; // Enable the PLL
// Step 4: Wait for the PLL to lock
/*
while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) {
// Optional: add a timeout mechanism here to avoid an infinite loop
}
*/
// Step 5: Configure the system clock dividers
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0U; // Set the system clock divider (0 = no division)
// Step 6: Enable PLL as the system clock source
//ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1U; // Enable PLL clock output
//Output clock setting for debugging
ClkCfgRegs.CLKSRCCTL3.bit.XCLKOUTSEL = 0U; // PLLSYSCLK
ClkCfgRegs.XCLKOUTDIVSEL.bit.XCLKOUTDIV = 0U; // No Prescalling
GpioCtrlRegs.GPAMUX2.bit.GPIO16= 0b11;
GpioCtrlRegs.GPAGMUX2.bit.GPIO16= 0b10;
EDIS;
}
void delay(volatile long count){
volatile long i;
// Simple delay loop
for(i = 0; i < count; i++);
}
